6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-25 16:31:42 +00:00
Code Issues Projects Releases Wiki Activity

Rethinks bitplane stops.

Browse Source
This commit is contained in:
Thomas Harte 2021-10-31 09:01:38 -07:00
parent 16f31cab6a
commit 4c1ab6ff25
2 changed files with 9 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
Machines/Amiga/Chipset.cpp
View File

@ -316,8 +316,11 @@ template <int cycle, bool stop_if_cpu> bool Chipset::perform_cycle() {
// Top priority: bitplane collection. // Top priority: bitplane collection.
// TODO: mask off fetch_window_'s lower bits. (Dependant on high/low-res?) // TODO: mask off fetch_window_'s lower bits. (Dependant on high/low-res?)
// Also: fetch_stop_ and that + 12/8 is the best I can discern from the Hardware Reference,
// but very obviously isn't how the actual hardware works. Explore on that.
fetch_horizontal_ |= cycle == fetch_window_[0]; fetch_horizontal_ |= cycle == fetch_window_[0];
horizontal_is_last_ |= cycle == fetch_window_[1]; if(cycle == fetch_window_[1]) fetch_stop_ = cycle + (is_high_res_ ? 12 : 8);
fetch_horizontal_ &= cycle != fetch_stop_;
if((dma_control_ & BitplaneFlag) == BitplaneFlag) { if((dma_control_ & BitplaneFlag) == BitplaneFlag) {
// TODO: offer a cycle for bitplane collection. // TODO: offer a cycle for bitplane collection.
// Probably need to indicate odd or even? // Probably need to indicate odd or even?
@ -459,7 +462,8 @@ template <bool stop_on_cpu> Chipset::Changes Chipset::run(HalfCycles length) {
previous_bitplanes_.clear(); previous_bitplanes_.clear();
} }
did_fetch_ = false; did_fetch_ = false;
fetch_horizontal_ = horizontal_is_last_ = false; fetch_horizontal_ = false;
fetch_stop_ = 0xffff;
if(y_ == frame_height_) { if(y_ == frame_height_) {
++vsyncs; ++vsyncs;
@ -514,8 +518,6 @@ void Chipset::post_bitplanes(const BitplaneData &data) {
even_delay_ even_delay_
); );
previous_bitplanes_ = data; previous_bitplanes_ = data;
fetch_horizontal_ &= !horizontal_is_last_;
} }
void Chipset::BitplaneShifter::set(const BitplaneData &previous, const BitplaneData &next, int odd_delay, int even_delay) { void Chipset::BitplaneShifter::set(const BitplaneData &previous, const BitplaneData &next, int odd_delay, int even_delay) {
@ -718,10 +720,10 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
case Write(0x094): // DDFSTOP case Write(0x094): // DDFSTOP
// TODO: something in my interpretation of ddfstart and ddfstop // TODO: something in my interpretation of ddfstart and ddfstop
// means a + 8 is needed below for high-res displays. Investigate. // means a + 8 is needed below for high-res displays. Investigate.
if(fetch_window_[1] != cycle.value16() + 8) { if(fetch_window_[1] != cycle.value16()) {
LOG("Fetch window stop set to " << std::dec << fetch_window_[1]); LOG("Fetch window stop set to " << std::dec << fetch_window_[1]);
} }
fetch_window_[1] = cycle.value16() + 8; fetch_window_[1] = cycle.value16();
break; break;
// Bitplanes. // Bitplanes.

2
Machines/Amiga/Chipset.hpp
View File

@ -201,9 +201,9 @@ class Chipset: private ClockingHint::Observer {
// Ephemeral bitplane collection state. // Ephemeral bitplane collection state.
bool fetch_vertical_ = false, fetch_horizontal_ = false; bool fetch_vertical_ = false, fetch_horizontal_ = false;
bool horizontal_is_last_ = false;
bool display_horizontal_ = false; bool display_horizontal_ = false;
bool did_fetch_ = false; bool did_fetch_ = false;
uint16_t fetch_stop_ = 0xffff;
// Output state. // Output state.
uint16_t border_colour_ = 0; uint16_t border_colour_ = 0;