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https://github.com/TomHarte/CLK.git
synced 2025-02-16 18:30:32 +00:00
Made first attempt to use the horizontal counter for something; here for sync timing only, even though I've gone exclusively with '81-style timing for now.
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@ -27,7 +27,20 @@ Machine::Machine() :
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}
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}
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int Machine::perform_machine_cycle(const CPU::Z80::MachineCycle &cycle) {
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int Machine::perform_machine_cycle(const CPU::Z80::MachineCycle &cycle) {
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int previous_counter = horizontal_counter_;
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horizontal_counter_ += cycle.length;
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if(previous_counter < 16 && horizontal_counter_ >= 16) {
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video_->run_for_cycles(16 - previous_counter);
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set_hsync(true);
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video_->run_for_cycles(horizontal_counter_ - 16);
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} else if(previous_counter < 32 && horizontal_counter_ >= 32) {
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video_->run_for_cycles(32 - previous_counter);
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set_hsync(false);
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video_->run_for_cycles(horizontal_counter_ - 32);
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} else {
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video_->run_for_cycles(cycle.length);
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video_->run_for_cycles(cycle.length);
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}
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// tape_player_.run_for_cycles(cycle.length);
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// tape_player_.run_for_cycles(cycle.length);
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uint16_t refresh = 0;
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uint16_t refresh = 0;
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@ -55,13 +68,14 @@ int Machine::perform_machine_cycle(const CPU::Z80::MachineCycle &cycle) {
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} break;
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} break;
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case CPU::Z80::BusOperation::Interrupt:
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case CPU::Z80::BusOperation::Interrupt:
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set_hsync(true);
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// set_hsync(true);
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line_counter_ = (line_counter_ + 1) & 7;
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line_counter_ = (line_counter_ + 1) & 7;
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*cycle.value = 0xff;
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*cycle.value = 0xff;
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horizontal_counter_ = 0; // TODO: more than this?
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break;
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break;
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case CPU::Z80::BusOperation::ReadOpcode:
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case CPU::Z80::BusOperation::ReadOpcode:
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set_hsync(false);
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// set_hsync(false);
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// The ZX80 and 81 signal an interrupt while refresh is active and bit 6 of the refresh
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// The ZX80 and 81 signal an interrupt while refresh is active and bit 6 of the refresh
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// address is low. The Z80 signals a refresh, providing the refresh address during the
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// address is low. The Z80 signals a refresh, providing the refresh address during the
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