From 4e25bcfcdcf6290c629c8121c6aef48d79a1543e Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Thu, 25 Apr 2019 14:19:13 -0400 Subject: [PATCH] Corrects decoding of AND/OR x, Dn. --- Processors/68000/Implementation/68000Storage.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Processors/68000/Implementation/68000Storage.cpp b/Processors/68000/Implementation/68000Storage.cpp index 3fc755228..385662446 100644 --- a/Processors/68000/Implementation/68000Storage.cpp +++ b/Processors/68000/Implementation/68000Storage.cpp @@ -894,8 +894,8 @@ struct ProcessorStorageConstructor { case l(PreDec): // [AND/OR/EOR].l Dn, -(An) op(int(Action::Decrement4) | MicroOp::DestinationMask, seq("n")); - case l(Ind): // [AND/OR/EOR].l Dn, (An)+ - case l(PostInc): // [AND/OR/EOR].l Dn, (An) + case l(Ind): // [AND/OR/EOR].l Dn, (An) + case l(PostInc): // [AND/OR/EOR].l Dn, (An)+ op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, seq("nRd+ nrd", { ea(1), ea(1) })); op(Action::PerformOperation, seq("np nw- nW", { ea(1), ea(1) })); if(mode == PostInc) { @@ -936,7 +936,7 @@ struct ProcessorStorageConstructor { storage_.instructions[instruction].set_source(storage_, ea_mode, ea_register); storage_.instructions[instruction].set_destination(storage_, Dn, data_register); - switch(mode) { + switch(is_long_word_access ? l(mode) : bw(mode)) { default: continue; case bw(Dn): // [AND/OR].bw Dn, Dn