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Do a de minimis checking of memory accesses.
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a2896b9bd0
commit
4e7a63f792
@ -64,13 +64,41 @@ struct Memory {
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struct MemoryLedger {
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template <typename IntT>
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bool write(uint32_t address, IntT source, Mode, bool) {
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return false; // TODO.
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if(write_pointer == writes.size() || writes[write_pointer].size != sizeof(IntT) || writes[write_pointer].address != address || writes[write_pointer].value != source) {
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throw 0;
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}
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++write_pointer;
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return true;
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}
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template <typename IntT>
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bool read(uint32_t address, IntT &source, Mode, bool) {
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return false; // TODO.
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if(read_pointer == reads.size() || reads[read_pointer].size != sizeof(IntT) || reads[read_pointer].address != address) {
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throw 0;
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}
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source = reads[read_pointer].value;
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++read_pointer;
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return true;
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}
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struct Access {
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size_t size;
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uint32_t address;
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uint32_t value;
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};
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template <typename IntT>
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void add_access(bool is_read, uint32_t address, IntT value) {
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auto &read = is_read ? reads.emplace_back() : writes.emplace_back();
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read.address = address;
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read.value = value;
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read.size = sizeof(IntT);
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}
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std::vector<Access> reads;
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std::vector<Access> writes;
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size_t read_pointer = 0;
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size_t write_pointer = 0;
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};
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}
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@ -339,7 +367,10 @@ struct MemoryLedger {
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execute<Model::ARMv2>(instruction, *test);
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for(uint32_t c = 0; c < 15; c++) {
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XCTAssertEqual(regs[c], registers[c]);
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XCTAssertEqual(
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regs[c],
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registers[c],
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@"R%d doesn't match during instruction %08x", c, instruction);
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}
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}
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continue;
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@ -353,21 +384,25 @@ struct MemoryLedger {
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if(label == "r.b") {
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// Capture a byte read for provision.
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test->bus.add_access<uint8_t>(true, address, value);
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continue;
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}
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if(label == "r.w") {
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// Capture a word read for provision.
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test->bus.add_access<uint32_t>(true, address, value);
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continue;
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}
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if(label == "w.b") {
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// Capture a byte write for comparison.
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test->bus.add_access<uint8_t>(false, address, value);
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continue;
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}
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if(label == "w.w") {
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// Capture a word write for comparison.
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test->bus.add_access<uint32_t>(false, address, value);
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continue;
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}
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}
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