mirror of
https://github.com/TomHarte/CLK.git
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Merge pull request #793 from TomHarte/Z80State
Adds reflective state for the Z80.
This commit is contained in:
Thomas Harte
GitHub
commit
4f30118b37
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@ -141,6 +141,8 @@
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4B15A9FD208249BB005E6C8D /* StaticAnalyser.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B15A9FA208249BB005E6C8D /* StaticAnalyser.cpp */; };
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4B17B58C20A8A9D9007CCA8F /* StringSerialiser.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B17B58920A8A9D9007CCA8F /* StringSerialiser.cpp */; };
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4B1B58F6246CC4E8009C171E /* State.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B1B58F4246CC4E8009C171E /* State.cpp */; };
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4B1B58F7246CC4E8009C171E /* State.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B1B58F4246CC4E8009C171E /* State.cpp */; };
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4B1B88BB202E2EC100B67DFF /* MultiKeyboardMachine.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B1B88B9202E2EC100B67DFF /* MultiKeyboardMachine.cpp */; };
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4B1B88BC202E2EC100B67DFF /* MultiKeyboardMachine.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B1B88B9202E2EC100B67DFF /* MultiKeyboardMachine.cpp */; };
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4B1B88BD202E3D3D00B67DFF /* MultiMachine.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4B3FCC3F201EC24200960631 /* MultiMachine.cpp */; };
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@ -984,6 +986,8 @@
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4B1667FB1FFF215F00A16032 /* KonamiWithSCC.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; name = KonamiWithSCC.hpp; path = MSX/Cartridges/KonamiWithSCC.hpp; sourceTree = "<group>"; };
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4B17B58920A8A9D9007CCA8F /* StringSerialiser.cpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.cpp; path = StringSerialiser.cpp; sourceTree = "<group>"; };
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4B17B58A20A8A9D9007CCA8F /* StringSerialiser.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = StringSerialiser.hpp; sourceTree = "<group>"; };
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4B1B58F4246CC4E8009C171E /* State.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = State.cpp; sourceTree = "<group>"; };
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4B1B58F5246CC4E8009C171E /* State.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = State.hpp; sourceTree = "<group>"; };
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4B1B88B9202E2EC100B67DFF /* MultiKeyboardMachine.cpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.cpp; path = MultiKeyboardMachine.cpp; sourceTree = "<group>"; };
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4B1B88BA202E2EC100B67DFF /* MultiKeyboardMachine.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = MultiKeyboardMachine.hpp; sourceTree = "<group>"; };
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4B1B88BE202E3DB200B67DFF /* MultiConfigurable.cpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.cpp; path = MultiConfigurable.cpp; sourceTree = "<group>"; };
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@ -2008,6 +2012,16 @@
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name = Cartridges;
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sourceTree = "<group>";
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};
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4B1B58F3246CC4E8009C171E /* State */ = {
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isa = PBXGroup;
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children = (
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4B1B58F4246CC4E8009C171E /* State.cpp */,
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4B1B58F5246CC4E8009C171E /* State.hpp */,
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);
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name = State;
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path = Z80/State;
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sourceTree = "<group>";
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};
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4B1E85791D174DEC001EF87D /* 6532 */ = {
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isa = PBXGroup;
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children = (
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@ -2630,6 +2644,7 @@
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4B77069C1EC904570053B588 /* Z80.hpp */,
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4B322DFC1F5A2981004EB04C /* AllRAM */,
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4B322DFF1F5A2981004EB04C /* Implementation */,
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4B1B58F3246CC4E8009C171E /* State */,
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);
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name = Z80;
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sourceTree = "<group>";
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@ -4441,6 +4456,7 @@
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4B055ACC1FAE9B030060FFFF /* Electron.cpp in Sources */,
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4B74CF822312FA9C00500CE8 /* HFV.cpp in Sources */,
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4B8318B022D3E531006DB630 /* AppleII.cpp in Sources */,
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4B1B58F7246CC4E8009C171E /* State.cpp in Sources */,
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4B0ACC03237756F6008902D0 /* Line.cpp in Sources */,
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4B055AB11FAE86070060FFFF /* Tape.cpp in Sources */,
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4BC1317B2346DF2B00E4FF3D /* MSA.cpp in Sources */,
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@ -4555,6 +4571,7 @@
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4B9BE400203A0C0600FFAE60 /* MultiSpeaker.cpp in Sources */,
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4B894538201967B4007DE474 /* Tape.cpp in Sources */,
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4B54C0CB1F8D92590050900F /* Keyboard.cpp in Sources */,
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4B1B58F6246CC4E8009C171E /* State.cpp in Sources */,
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4BEA525E1DF33323007E74F2 /* Tape.cpp in Sources */,
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4B2BF19623E10F0100C3AD60 /* CSHighPrecisionTimer.m in Sources */,
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4B8334951F5E25B60097E338 /* C1540.cpp in Sources */,
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@ -2,6 +2,6 @@
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<Workspace
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version = "1.0">
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<FileRef
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location = "self:Clock Signal.xcodeproj">
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location = "self:">
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</FileRef>
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</Workspace>
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@ -86,6 +86,7 @@ SOURCES += glob.glob('../../Processors/6502/Implementation/*.cpp')
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SOURCES += glob.glob('../../Processors/6502/State/*.cpp')
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SOURCES += glob.glob('../../Processors/68000/Implementation/*.cpp')
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SOURCES += glob.glob('../../Processors/Z80/Implementation/*.cpp')
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SOURCES += glob.glob('../../Processors/Z80/State/*.cpp')
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SOURCES += glob.glob('../../Reflection/*.cpp')
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@ -285,7 +285,7 @@ class ProcessorStorage {
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uint8_t irq_line_ = 0, irq_request_history_ = 0;
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bool nmi_line_is_enabled_ = false, set_overflow_line_is_enabled_ = false;
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// Allow state objects to capture and install state.
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// Allow state objects to capture and apply state.
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friend class State;
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};
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@ -11,7 +11,7 @@
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using namespace CPU::MOS6502;
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State::State(const ProcessorBase &src): State() {
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// Fill in registers.
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// Registers.
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registers.program_counter = src.pc_.full;
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registers.stack_pointer = src.s_;
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registers.flags = src.get_flags();
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@ -19,13 +19,13 @@ State::State(const ProcessorBase &src): State() {
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registers.x = src.x_;
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registers.y = src.y_;
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// Fill in other inputs.
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// Inputs.
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inputs.ready = src.ready_line_is_enabled_;
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inputs.irq = src.irq_line_;
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inputs.nmi = src.nmi_line_is_enabled_;
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inputs.reset = src.interrupt_requests_ & (ProcessorStorage::InterruptRequestFlags::Reset | ProcessorStorage::InterruptRequestFlags::PowerOn);
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// Fill in execution state.
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// Execution state.
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execution_state.operation = src.operation_;
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execution_state.operand = src.operand_;
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execution_state.address = src.address_.full;
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@ -51,7 +51,7 @@ State::State(const ProcessorBase &src): State() {
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}
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void State::apply(ProcessorBase &target) {
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// Grab registers.
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// Registers.
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target.pc_.full = registers.program_counter;
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target.s_ = registers.stack_pointer;
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target.set_flags(registers.flags);
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@ -59,13 +59,13 @@ void State::apply(ProcessorBase &target) {
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target.x_ = registers.x;
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target.y_ = registers.y;
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// Grab other inputs.
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// Inputs.
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target.ready_line_is_enabled_ = inputs.ready;
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target.set_irq_line(inputs.irq);
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target.set_nmi_line(inputs.nmi);
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target.set_reset_line(inputs.reset);
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// Set execution state.
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// Execution state.
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target.ready_is_active_ = target.is_jammed_ = target.wait_is_active_ = target.stop_is_active_ = false;
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switch(execution_state.phase) {
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case State::ExecutionState::Phase::Ready: target.ready_is_active_ = true; break;
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@ -1,13 +1,13 @@
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//
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// State.h
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// State.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 02/04/2020.
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// Copyright © 2020 Thomas Harte. All rights reserved.
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//
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#ifndef State_h
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#define State_h
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#ifndef State_hpp
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#define State_hpp
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#include "../../../Reflection/Enum.hpp"
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#include "../../../Reflection/Struct.hpp"
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@ -93,4 +93,4 @@ struct State: public Reflection::StructImpl<State> {
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}
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}
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#endif /* State_h */
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#endif /* State_hpp */
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@ -127,8 +127,6 @@ class ProcessorStorage {
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InstructionPage() : r_step(1), is_indexed(false) {}
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};
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typedef MicroOp InstructionTable[256][30];
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ProcessorStorage();
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void install_default_instruction_set();
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@ -195,8 +193,8 @@ class ProcessorStorage {
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@returns The current value of the flags register.
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*/
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uint8_t get_flags() {
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uint8_t result =
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uint8_t get_flags() const {
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return
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(sign_result_ & Flag::Sign) |
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(zero_result_ ? 0 : Flag::Zero) |
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(bit53_result_ & (Flag::Bit5 | Flag::Bit3)) |
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@ -204,7 +202,6 @@ class ProcessorStorage {
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(parity_overflow_result_ & Flag::Parity) |
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subtract_flag_ |
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(carry_result_ & Flag::Carry);
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return result;
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}
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/*!
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@ -224,6 +221,7 @@ class ProcessorStorage {
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carry_result_ = flags;
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}
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typedef MicroOp InstructionTable[256][30];
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virtual void assemble_page(InstructionPage &target, InstructionTable &table, bool add_offsets) = 0;
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virtual void copy_program(const MicroOp *source, std::vector<MicroOp> &destination) = 0;
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@ -232,4 +230,6 @@ class ProcessorStorage {
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void assemble_cb_page(InstructionPage &target, RegisterPair16 &index, bool add_offsets);
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void assemble_base_page(InstructionPage &target, RegisterPair16 &index, bool add_offsets, InstructionPage &cb_page);
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// Allos state objects to capture and apply state.
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friend class State;
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};
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222
Processors/Z80/State/State.cpp
Normal file
222
Processors/Z80/State/State.cpp
Normal file
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@ -0,0 +1,222 @@
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//
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// State.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 13/05/2020.
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// Copyright © 2020 Thomas Harte. All rights reserved.
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//
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#include "State.hpp"
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#include <cassert>
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using namespace CPU::Z80;
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State::State(const ProcessorBase &src): State() {
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// Registers.
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registers.a = src.a_;
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registers.flags = src.get_flags();
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registers.bc = src.bc_.full;
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registers.de = src.de_.full;
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registers.hl = src.hl_.full;
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registers.bcDash = src.bcDash_.full;
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registers.deDash = src.deDash_.full;
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registers.hlDash = src.hlDash_.full;
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registers.ix = src.ix_.full;
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registers.iy = src.iy_.full;
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registers.ir = src.ir_.full;
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registers.program_counter = src.pc_.full;
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registers.stack_pointer = src.sp_.full;
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registers.memptr = src.memptr_.full;
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registers.interrupt_mode = src.interrupt_mode_;
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registers.iff1 = src.iff1_;
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registers.iff2 = src.iff2_;
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// Inputs.
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inputs.irq = src.irq_line_;
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inputs.nmi = src.nmi_line_;
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inputs.wait = src.wait_line_;
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inputs.bus_request = src.bus_request_line_;
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// Execution State.
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execution_state.is_halted = src.halt_mask_ == 0x00;
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execution_state.requests = src.request_status_;
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execution_state.last_requests = src.last_request_status_;
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execution_state.temp8 = src.temp8_;
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execution_state.temp16 = src.temp16_.full;
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execution_state.operation = src.operation_;
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execution_state.flag_adjustment_history = src.flag_adjustment_history_;
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execution_state.pc_increment = src.pc_increment_;
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execution_state.refresh_address = src.refresh_addr_.full;
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execution_state.half_cycles_into_step = src.number_of_cycles_.as<int>();
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// Search for the current holder of the scheduled_program_counter_.
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#define ContainedBy(x) (src.scheduled_program_counter_ >= &src.x[0]) && (src.scheduled_program_counter_ < &src.x[src.x.size()])
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#define Populate(x, y) \
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execution_state.phase = ExecutionState::Phase::x; \
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execution_state.steps_into_phase = int(src.scheduled_program_counter_ - &src.y[0]);
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if(ContainedBy(conditional_call_untaken_program_)) {
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Populate(UntakenConditionalCall, conditional_call_untaken_program_);
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} else if(ContainedBy(reset_program_)) {
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Populate(Reset, reset_program_);
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} else if(ContainedBy(irq_program_[0])) {
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Populate(IRQMode0, irq_program_[0]);
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} else if(ContainedBy(irq_program_[1])) {
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Populate(IRQMode1, irq_program_[1]);
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} else if(ContainedBy(irq_program_[2])) {
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Populate(IRQMode2, irq_program_[2]);
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} else if(ContainedBy(nmi_program_)) {
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Populate(NMI, nmi_program_);
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} else {
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if(src.current_instruction_page_ == &src.base_page_) {
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execution_state.instruction_page = 0;
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} else if(src.current_instruction_page_ == &src.ed_page_) {
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execution_state.instruction_page = 0xed;
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} else if(src.current_instruction_page_ == &src.fd_page_) {
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execution_state.instruction_page = 0xfd;
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} else if(src.current_instruction_page_ == &src.dd_page_) {
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execution_state.instruction_page = 0xdd;
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} else if(src.current_instruction_page_ == &src.cb_page_) {
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execution_state.instruction_page = 0xcb;
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} else if(src.current_instruction_page_ == &src.fdcb_page_) {
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execution_state.instruction_page = 0xfdcb;
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} else if(src.current_instruction_page_ == &src.ddcb_page_) {
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execution_state.instruction_page = 0xddcb;
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}
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if(ContainedBy(current_instruction_page_->fetch_decode_execute)) {
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Populate(FetchDecode, current_instruction_page_->fetch_decode_execute);
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} else {
|
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// There's no need to determine which opcode because that knowledge is already
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// contained in the dedicated opcode field.
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Populate(Operation, current_instruction_page_->instructions[src.operation_ & src.halt_mask_]);
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}
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}
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assert(execution_state.steps_into_phase >= 0);
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#undef Populate
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#undef ContainedBy
|
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}
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void State::apply(ProcessorBase &target) {
|
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// Registers.
|
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target.a_ = registers.a;
|
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target.set_flags(registers.flags);
|
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target.bc_.full = registers.bc;
|
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target.de_.full = registers.de;
|
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target.hl_.full = registers.hl;
|
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target.bcDash_.full = registers.bcDash;
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target.deDash_.full = registers.deDash;
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target.hlDash_.full = registers.hlDash;
|
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target.ix_.full = registers.ix;
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target.iy_.full = registers.iy;
|
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target.ir_.full = registers.ir;
|
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target.pc_.full = registers.program_counter;
|
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target.sp_.full = registers.stack_pointer;
|
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target.memptr_.full = registers.memptr;
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target.interrupt_mode_ = registers.interrupt_mode;
|
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target.iff1_ = registers.iff1;
|
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target.iff2_ = registers.iff2;
|
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|
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// Inputs.
|
||||
target.irq_line_ = inputs.irq;
|
||||
target.nmi_line_ = inputs.nmi;
|
||||
target.wait_line_ = inputs.wait;
|
||||
target.bus_request_line_ = inputs.bus_request;
|
||||
|
||||
// Execution State.
|
||||
target.halt_mask_ = execution_state.is_halted ? 0x00 : 0xff;
|
||||
target.request_status_ = execution_state.requests;
|
||||
target.last_request_status_ = execution_state.last_requests;
|
||||
target.temp8_ = execution_state.temp8;
|
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target.temp16_.full = execution_state.temp16;
|
||||
target.operation_ = execution_state.operation;
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target.flag_adjustment_history_ = execution_state.flag_adjustment_history;
|
||||
target.pc_increment_ = execution_state.pc_increment;
|
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target.refresh_addr_.full = execution_state.refresh_address;
|
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target.number_of_cycles_ = HalfCycles(execution_state.half_cycles_into_step);
|
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|
||||
switch(execution_state.instruction_page) {
|
||||
default: target.current_instruction_page_ = &target.base_page_; break;
|
||||
case 0xed: target.current_instruction_page_ = &target.ed_page_; break;
|
||||
case 0xdd: target.current_instruction_page_ = &target.dd_page_; break;
|
||||
case 0xcb: target.current_instruction_page_ = &target.cb_page_; break;
|
||||
case 0xfd: target.current_instruction_page_ = &target.fd_page_; break;
|
||||
case 0xfdcb: target.current_instruction_page_ = &target.fdcb_page_; break;
|
||||
case 0xddcb: target.current_instruction_page_ = &target.ddcb_page_; break;
|
||||
}
|
||||
|
||||
switch(execution_state.phase) {
|
||||
case ExecutionState::Phase::UntakenConditionalCall: target.scheduled_program_counter_ = &target.conditional_call_untaken_program_[0]; break;
|
||||
case ExecutionState::Phase::Reset: target.scheduled_program_counter_ = &target.reset_program_[0]; break;
|
||||
case ExecutionState::Phase::IRQMode0: target.scheduled_program_counter_ = &target.irq_program_[0][0]; break;
|
||||
case ExecutionState::Phase::IRQMode1: target.scheduled_program_counter_ = &target.irq_program_[1][0]; break;
|
||||
case ExecutionState::Phase::IRQMode2: target.scheduled_program_counter_ = &target.irq_program_[2][0]; break;
|
||||
case ExecutionState::Phase::NMI: target.scheduled_program_counter_ = &target.nmi_program_[0]; break;
|
||||
case ExecutionState::Phase::FetchDecode: target.scheduled_program_counter_ = &target.current_instruction_page_->fetch_decode_execute[0]; break;
|
||||
case ExecutionState::Phase::Operation: target.scheduled_program_counter_ = target.current_instruction_page_->instructions[target.operation_]; break;
|
||||
}
|
||||
target.scheduled_program_counter_ += execution_state.steps_into_phase;
|
||||
}
|
||||
|
||||
// Boilerplate follows here, to establish 'reflection'.
|
||||
State::State() {
|
||||
if(needs_declare()) {
|
||||
DeclareField(registers);
|
||||
DeclareField(execution_state);
|
||||
DeclareField(inputs);
|
||||
}
|
||||
}
|
||||
|
||||
State::Registers::Registers() {
|
||||
if(needs_declare()) {
|
||||
DeclareField(a);
|
||||
DeclareField(flags);
|
||||
DeclareField(bc);
|
||||
DeclareField(de);
|
||||
DeclareField(hl);
|
||||
DeclareField(bcDash);
|
||||
DeclareField(deDash);
|
||||
DeclareField(hlDash);
|
||||
DeclareField(ix);
|
||||
DeclareField(iy);
|
||||
DeclareField(ir);
|
||||
DeclareField(program_counter);
|
||||
DeclareField(stack_pointer);
|
||||
DeclareField(interrupt_mode);
|
||||
DeclareField(iff1);
|
||||
DeclareField(iff2);
|
||||
DeclareField(memptr);
|
||||
}
|
||||
}
|
||||
|
||||
State::ExecutionState::ExecutionState() {
|
||||
if(needs_declare()) {
|
||||
DeclareField(is_halted);
|
||||
DeclareField(requests);
|
||||
DeclareField(last_requests);
|
||||
DeclareField(temp8);
|
||||
DeclareField(operation);
|
||||
DeclareField(temp16);
|
||||
DeclareField(flag_adjustment_history);
|
||||
DeclareField(pc_increment);
|
||||
DeclareField(refresh_address);
|
||||
|
||||
AnnounceEnum(Phase);
|
||||
DeclareField(phase);
|
||||
DeclareField(half_cycles_into_step);
|
||||
DeclareField(steps_into_phase);
|
||||
DeclareField(instruction_page);
|
||||
}
|
||||
}
|
||||
|
||||
State::Inputs::Inputs() {
|
||||
if(needs_declare()) {
|
||||
DeclareField(irq);
|
||||
DeclareField(nmi);
|
||||
DeclareField(bus_request);
|
||||
DeclareField(wait);
|
||||
}
|
||||
}
|
||||
100
Processors/Z80/State/State.hpp
Normal file
100
Processors/Z80/State/State.hpp
Normal file
|
|
@ -0,0 +1,100 @@
|
|||
//
|
||||
// State.hpp
|
||||
// Clock Signal
|
||||
//
|
||||
// Created by Thomas Harte on 13/05/2020.
|
||||
// Copyright © 2020 Thomas Harte. All rights reserved.
|
||||
//
|
||||
|
||||
#ifndef State_hpp
|
||||
#define State_hpp
|
||||
|
||||
#include "../../../Reflection/Enum.hpp"
|
||||
#include "../../../Reflection/Struct.hpp"
|
||||
#include "../Z80.hpp"
|
||||
|
||||
namespace CPU {
|
||||
namespace Z80 {
|
||||
|
||||
/*!
|
||||
Provides a means for capturing or restoring complete Z80 state.
|
||||
|
||||
This is an optional adjunct to the Z80 class. If you want to take the rest of the Z80
|
||||
implementation but don't want any of the overhead of my sort-of half-reflection as
|
||||
encapsulated in Reflection/[Enum/Struct].hpp just don't use this class.
|
||||
*/
|
||||
struct State: public Reflection::StructImpl<State> {
|
||||
/*!
|
||||
Provides the current state of the well-known, published internal registers.
|
||||
*/
|
||||
struct Registers: public Reflection::StructImpl<Registers> {
|
||||
uint8_t a;
|
||||
uint8_t flags;
|
||||
uint16_t bc, de, hl;
|
||||
uint16_t bcDash, deDash, hlDash;
|
||||
uint16_t ix, iy, ir;
|
||||
uint16_t program_counter, stack_pointer;
|
||||
uint16_t memptr;
|
||||
int interrupt_mode;
|
||||
bool iff1, iff2;
|
||||
|
||||
Registers();
|
||||
} registers;
|
||||
|
||||
/*!
|
||||
Provides the current state of the processor's various input lines that aren't
|
||||
related to an access cycle.
|
||||
*/
|
||||
struct Inputs: public Reflection::StructImpl<Inputs> {
|
||||
bool irq = false;
|
||||
bool nmi = false;
|
||||
bool bus_request = false;
|
||||
bool wait = false;
|
||||
|
||||
Inputs();
|
||||
} inputs;
|
||||
|
||||
/*!
|
||||
Contains internal state used by this particular implementation of a 6502. Most of it
|
||||
does not necessarily correlate with anything in a real 6502, and some of it very
|
||||
obviously doesn't.
|
||||
*/
|
||||
struct ExecutionState: public Reflection::StructImpl<ExecutionState> {
|
||||
bool is_halted;
|
||||
|
||||
uint8_t requests;
|
||||
uint8_t last_requests;
|
||||
uint8_t temp8;
|
||||
uint8_t operation;
|
||||
uint16_t temp16;
|
||||
unsigned int flag_adjustment_history;
|
||||
uint16_t pc_increment;
|
||||
uint16_t refresh_address;
|
||||
|
||||
ReflectableEnum(Phase,
|
||||
UntakenConditionalCall, Reset, IRQMode0, IRQMode1, IRQMode2,
|
||||
NMI, FetchDecode, Operation
|
||||
);
|
||||
|
||||
Phase phase;
|
||||
int half_cycles_into_step;
|
||||
int steps_into_phase;
|
||||
uint16_t instruction_page = 0;
|
||||
|
||||
ExecutionState();
|
||||
} execution_state;
|
||||
|
||||
/// Default constructor; makes no guarantees as to field values beyond those given above.
|
||||
State();
|
||||
|
||||
/// Instantiates a new State based on the processor @c src.
|
||||
State(const ProcessorBase &src);
|
||||
|
||||
/// Applies this state to @c target.
|
||||
void apply(ProcessorBase &target);
|
||||
};
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* State_hpp */
|
||||
|
|
@ -11,6 +11,7 @@
|
|||
#include <algorithm>
|
||||
#include <iomanip>
|
||||
#include <sstream>
|
||||
#include <type_traits>
|
||||
|
||||
// MARK: - Setters
|
||||
|
||||
|
|
@ -113,11 +114,20 @@ template <typename Type> bool Reflection::get(const Struct &target, const std::s
|
|||
const auto target_type = target.type_of(name);
|
||||
if(!target_type) return false;
|
||||
|
||||
// If type is a direct match, copy.
|
||||
if(*target_type == typeid(Type)) {
|
||||
memcpy(&value, target.get(name), sizeof(Type));
|
||||
return true;
|
||||
}
|
||||
|
||||
// If the type is a registered enum and the value type is int, copy.
|
||||
if constexpr (std::is_integral<Type>::value && sizeof(Type) == sizeof(int)) {
|
||||
if(!Enum::name(*target_type).empty()) {
|
||||
memcpy(&value, target.get(name), sizeof(int));
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user