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https://github.com/TomHarte/CLK.git
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Eliminates the optionality of a DPLL receiver.
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@@ -20,12 +20,13 @@ Storage::Disk::PCMSegment Storage::Disk::track_serialisation(const Track &track,
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// its PCMSegment.
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struct ResultAccumulator {
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PCMSegment result;
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bool is_recording = false;
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void digital_phase_locked_loop_output_bit(int value) {
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result.data.push_back(!!value);
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if(is_recording) result.data.push_back(!!value);
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}
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} result_accumulator;
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result_accumulator.result.length_of_a_bit = length_of_a_bit;
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DigitalPhaseLockedLoop<ResultAccumulator> pll(100);
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DigitalPhaseLockedLoop<ResultAccumulator> pll(100, result_accumulator);
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// Obtain a length multiplier which is 100 times the reciprocal
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// of the expected bit length. So a perfect bit length from
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@@ -55,7 +56,7 @@ Storage::Disk::PCMSegment Storage::Disk::track_serialisation(const Track &track,
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if(!history_size) {
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track_copy->seek_to(Time(0));
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time_error.set_zero();
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pll.set_delegate(&result_accumulator);
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result_accumulator.is_recording = true;
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}
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}
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}
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