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https://github.com/TomHarte/CLK.git
synced 2024-11-21 21:33:54 +00:00
Fix faulty centring.
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parent
0efe649ca5
commit
51c8396e32
@ -23,7 +23,7 @@ VideoOutput::VideoOutput(const uint8_t *memory) :
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crt_.set_visible_area(crt_.get_rect_for_area(
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312 - vsync_end,
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256,
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h_total - hsync_end,
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h_total - hsync_start,
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80 * 8,
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4.0f / 3.0f
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));
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@ -56,18 +56,10 @@ uint8_t VideoOutput::run_for(const Cycles cycles) {
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// reverse-engineering of the Electron ULA. It should therefore be as accurate to the
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// original hardware as my comprehension of VHDL and adaptation into sequential code allows.
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// Horizontal and vertical counter updates; code below should act
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const bool is_v_end = this->is_v_end();
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h_count_ += 8;
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if(h_count_ == h_total) {
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h_count_ = 0;
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++v_count_;
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if(is_v_end) {
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v_count_ = 0;
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field_ = !field_;
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}
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}
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// In this, the sequential world of C++, all tests below should assume that the position
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// named by (h_count_, v_count_) is the one that was active **prior to this cycle**.
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//
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// So this cycle spans the period from (h_count_, v_count_) to (h_count_, v_count_)+1.
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// Test for interrupts.
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if(v_count_ == v_rtc && ((!field_ && !h_count_) || (field_ && h_count_ == h_half))) {
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@ -100,7 +92,7 @@ uint8_t VideoOutput::run_for(const Cycles cycles) {
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// Update character row on the trailing edge of hsync.
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if(h_count_ == hsync_end) {
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if(is_v_end) {
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if(is_v_end()) {
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char_row_ = 0;
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} else {
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char_row_ = last_line() ? 0 : char_row_ + 1;
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@ -113,7 +105,7 @@ uint8_t VideoOutput::run_for(const Cycles cycles) {
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}
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// Latch video address at frame start.
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if(h_count_ == h_reset_addr && is_v_end) {
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if(h_count_ == h_reset_addr && is_v_end()) {
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row_addr_ = byte_addr_ = screen_base_;
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}
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@ -206,6 +198,19 @@ uint8_t VideoOutput::run_for(const Cycles cycles) {
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}
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}
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}
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// Horizontal and vertical counter updates; code below should act
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h_count_ += 8;
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if(h_count_ == h_total) {
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h_count_ = 0;
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if(is_v_end()) {
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v_count_ = 0;
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field_ = !field_;
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} else {
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++v_count_;
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}
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}
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}
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return interrupts;
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