From dc30581be0d9680356f7f4ef573e36b1c18ef4a1 Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Mon, 28 Mar 2022 16:39:55 -0400 Subject: [PATCH 1/3] Fix typo; . -> , --- InstructionSets/PowerPC/Instruction.hpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/InstructionSets/PowerPC/Instruction.hpp b/InstructionSets/PowerPC/Instruction.hpp index 7d801adc1..f70aca97c 100644 --- a/InstructionSets/PowerPC/Instruction.hpp +++ b/InstructionSets/PowerPC/Instruction.hpp @@ -134,7 +134,7 @@ enum class Operation: uint8_t { addx, /// Add carrying. - /// addc. addc., addco, addco. + /// addc, addc., addco, addco. /// /// rD() = rA() + rB(). XER[CA] is set if a carry occurs. /// oe() and rc() apply. From 0a453550551019d2d8a67d26b84943e0428a2e17 Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Tue, 29 Mar 2022 14:37:21 -0400 Subject: [PATCH 2/3] Add a few more field comments. --- InstructionSets/PowerPC/Instruction.hpp | 44 +++++++++++++++++++++---- 1 file changed, 38 insertions(+), 6 deletions(-) diff --git a/InstructionSets/PowerPC/Instruction.hpp b/InstructionSets/PowerPC/Instruction.hpp index f70aca97c..2d76ca8f7 100644 --- a/InstructionSets/PowerPC/Instruction.hpp +++ b/InstructionSets/PowerPC/Instruction.hpp @@ -136,8 +136,9 @@ enum class Operation: uint8_t { /// Add carrying. /// addc, addc., addco, addco. /// - /// rD() = rA() + rB(). XER[CA] is set if a carry occurs. - /// oe() and rc() apply. + /// rD() = rA() + rB(). + /// XER[CA] is updated with carry; if oe() is set then so are XER[SO] and XER[OV]. + /// if rc() is set, LT, GT, EQ and SO condition bits are updated. addcx, /// Add extended. @@ -185,8 +186,23 @@ enum class Operation: uint8_t { /// /// rD() = rA() + XER[CA] /// oe() and rc() apply. - addzex, andx, - andcx, andi_, andis_, + addzex, + + /// And. + /// and, and. + andx, + + /// And with complement. + /// andc, andc. + andcx, + + /// And immediate. + /// andi. + andi_, + + /// And immediate shifted. + /// andis. + andis_, /// Branch unconditional. /// b, bl, ba, bla @@ -222,7 +238,11 @@ enum class Operation: uint8_t { /// aa(), bi(), bo() and lk() are as per bcx. bclrx, - cmp, cmpi, cmpl, cmpli, + /// Compare. + /// cmp + cmp, + + cmpi, cmpl, cmpli, cntlzwx, crand, crandc, creqv, crnand, crnor, cror, crorc, crxor, dcbf, dcbst, dcbt, dcbtst, dcbz, divwx, divwux, eciwx, ecowx, eieio, eqvx, extsbx, extshx, fabsx, faddx, faddsx, fcmpo, fcmpu, fctiwx, fctiwzx, @@ -276,7 +296,19 @@ enum class Operation: uint8_t { nandx, negx, norx, orx, orcx, ori, oris, rfi, rlwimix, rlwinmx, rlwnmx, sc, slwx, srawx, srawix, srwx, stb, stbu, stbux, stbx, stfd, stfdu, stfdux, stfdx, stfs, stfsu, stfsux, stfsx, sth, sthbrx, sthu, sthux, sthx, - stmw, stswi, stswx, stw, stwbrx, stwcx_, stwu, stwux, stwx, subfx, subfcx, + stmw, stswi, stswx, stw, stwbrx, stwcx_, stwu, + + /// Store word with update indexed. + /// stwux + /// + /// rS(), rA(), rB() + stwux, + + /// Store word indexed. + /// stwx + /// + /// rS(), rA(), rB() + stwx, subfx, subfcx, subfex, subfic, subfmex, subfzex, sync, tw, twi, xorx, xori, xoris, mftb, // From d78397559786ae48744bd4a00ec7fa933becd4c7 Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Tue, 29 Mar 2022 19:59:21 -0400 Subject: [PATCH 3/3] Start offering a list of relevant fields per Operation. --- InstructionSets/PowerPC/Instruction.hpp | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/InstructionSets/PowerPC/Instruction.hpp b/InstructionSets/PowerPC/Instruction.hpp index e5b8c2165..2d1787b90 100644 --- a/InstructionSets/PowerPC/Instruction.hpp +++ b/InstructionSets/PowerPC/Instruction.hpp @@ -73,6 +73,7 @@ enum class Operation: uint8_t { /// Absolute. /// abs, abs., abso, abso. + /// rA(), rD(), oe() /// /// |rA| is placed into rD. If rA = 0x8000'0000 then 0x8000'0000 is placed into rD /// and XER[OV] is set if oe() indicates that overflow is enabled. @@ -80,6 +81,7 @@ enum class Operation: uint8_t { /// Cache line compute size. /// clcs + /// rA(), rD() /// /// The size of the cache line specified by rA is placed into rD. Cf. the CacheLine enum. /// As an aside: all cache lines are 64 bytes on the MPC601. @@ -87,6 +89,7 @@ enum class Operation: uint8_t { /// Divide. /// div, div., divo, divo. + /// rA(), rB(), rD(), rc(), oe() /// /// Unsigned 64-bit divide. rA|MQ / rB is placed into rD and the /// remainder is placed into MQ. The ermainder has the same sign as the dividend @@ -98,6 +101,7 @@ enum class Operation: uint8_t { /// Divide short. /// divs, divs., divso, divso. + /// rA(), rB(), rD(), rc(), eo() /// /// Signed 32-bit divide. rD = rA/rB; remainder is /// placed into MQ. The ermainder has the same sign as the dividend @@ -109,12 +113,14 @@ enum class Operation: uint8_t { /// Difference or zero. /// dozi + /// rA(), rB(), rD() /// /// if rA > rB then rD = 0; else rD = NOT(rA) + rB + 1. dozx, /// Difference or zero immediate. /// dozi + /// rA(), rD(), simm() /// /// if rA > simm() then rD = 0; else rD = NOT(rA) + simm() + 1. dozi, @@ -129,12 +135,14 @@ enum class Operation: uint8_t { /// Add. /// add, add., addo, addo. + /// rA(), rB(), rD(), rc(), oe() /// /// rD() = rA() + rB(). Carry is ignored, rD() may be equal to rA() or rB(). addx, /// Add carrying. /// addc, addc., addco, addco. + /// rA(), rB(), rD(), rc(), oe() /// /// rD() = rA() + rB(). /// XER[CA] is updated with carry; if oe() is set then so are XER[SO] and XER[OV]. @@ -143,6 +151,7 @@ enum class Operation: uint8_t { /// Add extended. /// adde, adde., addeo, addeo. + /// rA(), rB(), rD(), rc(), eo() /// /// rD() = rA() + rB() + XER[CA]; XER[CA] is set if further carry occurs. /// oe() and rc() apply. @@ -150,12 +159,14 @@ enum class Operation: uint8_t { /// Add immediate. /// addi + /// rA(), rD(), simm() /// /// rD() = (rA() | 0) + simm() addi, /// Add immediate carrying. /// addic + /// rA(), rD(), simm() /// /// rD() = (rA() | 0) + simm() /// XER[CA] is updated. @@ -163,6 +174,7 @@ enum class Operation: uint8_t { /// Add immediate carrying and record. /// addic. + /// rA(), rD(), simm() /// /// rD() = (rA() | 0) + simm() /// XER[CA] and the condition register are updated. @@ -170,42 +182,48 @@ enum class Operation: uint8_t { /// Add immediate shifted. /// addis. + /// rA(), rD(), simm() /// /// rD() = (rA() | 0) + (simm() << 16) addis, /// Add to minus one. /// addme, addme., addmeo, addmeo. + /// rA(), rD(), rc(), oe() /// /// rD() = rA() + XER[CA] + 0xffff'ffff - /// oe() and rc() apply. addmex, /// Add to zero extended. /// addze, addze., addzeo, addzeo. + /// rA(), rD(), rc(), oe() /// /// rD() = rA() + XER[CA] - /// oe() and rc() apply. addzex, /// And. /// and, and. + /// rA(), rB(), rD(), rc() andx, /// And with complement. /// andc, andc. + /// rA(), rB(), rD(), rc() andcx, /// And immediate. /// andi. + /// rA(), rD(), uimm() andi_, /// And immediate shifted. /// andis. + /// rA(), rD(), uimm() andis_, /// Branch unconditional. /// b, bl, ba, bla + /// aa(), li(), lk() /// /// Use li() to get the included immediate value. /// @@ -215,6 +233,7 @@ enum class Operation: uint8_t { /// Branch conditional. /// bne, bne+, beq, bdnzt+, bdnzf, bdnzt, bdnzfla ... + /// aa(), lk(), bd(), bi(), bo() /// /// aa() determines whether the branch has a relative or absolute target. /// lk() determines whether to update the link register. @@ -225,6 +244,7 @@ enum class Operation: uint8_t { /// Branch conditional to count register. /// bctr, bctrl, bnectrl, bnectrl, bltctr, blectr ... + /// aa(), lk(), bi(), bo() /// /// aa(), bi(), bo() and lk() are as per bcx. /// @@ -234,6 +254,7 @@ enum class Operation: uint8_t { /// Branch conditional to link register. /// blr, blrl, bltlr, blelrl, bnelrl ... + /// aa(), lk(), bi(), bo() /// /// aa(), bi(), bo() and lk() are as per bcx. bclrx,