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mirror of https://github.com/TomHarte/CLK.git synced 2024-11-23 03:32:32 +00:00

Improved test reporting, attempted to resolve timing errors just introduced (i.e. to differentiate break/continue where a cycle may or may not be spent).

This commit is contained in:
Thomas Harte 2016-10-27 08:41:44 -04:00
parent f84b66a5f4
commit 534b3d085d
2 changed files with 7 additions and 4 deletions

View File

@ -217,7 +217,7 @@ class MOS6502TimingTests: XCTestCase, CSTestMachineJamHandler {
machine.runForNumber(ofCycles: 10)
}
XCTAssert(self.endTime == expectedRunLength, "Took \(self.endTime) cycles to perform")
XCTAssert(self.endTime == expectedRunLength, "Took \(self.endTime) cycles to perform rather than \(expectedRunLength)")
}
func testMachine(_ machine: CSTestMachine!, didJamAtAddress address: UInt16) {

View File

@ -964,8 +964,9 @@ template <class T> class Processor {
_address.bytes.low = nextAddress.bytes.low;
if(_address.bytes.high != nextAddress.bytes.high) {
throwaway_read(_address.full);
}
break;
}
continue;
case CycleAddXToAddressLowRead:
nextAddress.full = _address.full + _x;
_address.bytes.low = nextAddress.bytes.low;
@ -976,8 +977,9 @@ template <class T> class Processor {
_address.bytes.low = nextAddress.bytes.low;
if(_address.bytes.high != nextAddress.bytes.high) {
throwaway_read(_address.full);
}
break;
}
continue;
case CycleAddYToAddressLowRead:
nextAddress.full = _address.full + _y;
_address.bytes.low = nextAddress.bytes.low;
@ -1061,8 +1063,9 @@ template <class T> class Processor {
uint16_t halfUpdatedPc = _pc.full;
_pc.full = nextAddress.full;
throwaway_read(halfUpdatedPc);
}
break;
}
continue;
#undef BRA