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Imports CMP tests, and fixes CMP.l timing.
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@ -1981,6 +1981,78 @@ class CPU::MC68000::ProcessorStorageTests {
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XCTAssertEqual(20, _machine->get_cycle_count());
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}
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// MARK: CMP
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- (void)performCMPb:(uint16_t)opcode expectedFlags:(uint16_t)flags {
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_machine->set_program({
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opcode
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});
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auto state = _machine->get_processor_state();
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state.data[1] = 0x1234567f;
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state.data[2] = 0x12345680;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[1], 0x1234567f);
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XCTAssertEqual(state.data[2], 0x12345680);
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XCTAssertEqual(state.status & Flag::ConditionCodes, flags);
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XCTAssertEqual(4, _machine->get_cycle_count());
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}
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- (void)testCMPb_D1D2 {
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[self performCMPb:0xb401 expectedFlags:Flag::Overflow]; // CMP.b D1, D2
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}
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- (void)testCMPb_D2D1 {
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[self performCMPb:0xb202 expectedFlags:Flag::Overflow | Flag::Negative | Flag::Carry]; // CMP.b D2, D1
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}
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- (void)performCMPwd1:(uint32_t)d1 d2:(uint32_t)d2 expectedFlags:(uint16_t)flags {
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_machine->set_program({
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0xb242 // CMP.W D2, D1
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});
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auto state = _machine->get_processor_state();
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state.data[1] = d1;
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state.data[2] = d2;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[1], d1);
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XCTAssertEqual(state.data[2], d2);
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XCTAssertEqual(state.status & Flag::ConditionCodes, flags);
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XCTAssertEqual(4, _machine->get_cycle_count());
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}
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- (void)testCMPw_8004v7002 {
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[self performCMPwd1:0x12347002 d2:0x12348004 expectedFlags:Flag::Overflow | Flag::Negative | Flag::Carry];
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}
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- (void)testCMPw_6666v5555 {
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[self performCMPwd1:0x55555555 d2:0x66666666 expectedFlags:Flag::Negative | Flag::Carry];
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}
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- (void)testCMPl {
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_machine->set_program({
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0xb282 // CMP.l D2, D1
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});
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auto state = _machine->get_processor_state();
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state.data[1] = 0x12347002;
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state.data[2] = 0x12348004;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[1], 0x12347002);
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XCTAssertEqual(state.data[2], 0x12348004);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Carry);
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XCTAssertEqual(6, _machine->get_cycle_count());
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}
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// MARK: CMPA
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- (void)performCMPAld1:(uint32_t)d1 a2:(uint32_t)a2 {
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@ -2027,12 +2027,15 @@ struct ProcessorStorageConstructor {
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default: continue;
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case bw(Dn): // CMP.bw Dn, Dn
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case l(Dn): // CMP.l Dn, Dn
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case bw(An): // CMP.w An, Dn
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case l(An): // CMP.l An, Dn
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op(Action::PerformOperation, seq("np"));
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break;
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case l(Dn): // CMP.l Dn, Dn
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case l(An): // CMP.l An, Dn
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op(Action::PerformOperation, seq("np n"));
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break;
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case bw(Ind): // CMP.bw (An), Dn
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case bw(PostInc): // CMP.bw (An)+, Dn
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op(Action::None, seq("nr np", { a(ea_register) }, !is_byte_access));
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