6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-26 08:49:37 +00:00
Code Issues Projects Releases Wiki Activity

Further fixes PEA, and OR/AND/EOR Dn, (An).

Browse Source
This commit is contained in:
Thomas Harte 2019-05-29 14:37:15 -04:00
parent 77b08febdb
commit 541b75ee6e
3 changed files with 11 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Processors/68000/Implementation/68000Implementation.hpp
View File

@ -279,7 +279,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
} }
#ifdef LOG_TRACE #ifdef LOG_TRACE
should_log |= ((program_counter_.full - 4) == 0x4058dc); // 0x40103e should_log |= (program_counter_.full - 4) == 0x405350;
#endif #endif
if(instructions[decoded_instruction_.full].micro_operations) { if(instructions[decoded_instruction_.full].micro_operations) {
@ -803,6 +803,10 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
active_program_->destination->full = active_program_->source->full; active_program_->destination->full = active_program_->source->full;
break; break;
case Operation::PEA:
destination_bus_data_[0] = effective_address_[0];
break;
/* /*
Status word moves and manipulations. Status word moves and manipulations.
*/ */

12
Processors/68000/Implementation/68000Storage.cpp
View File

@ -606,7 +606,7 @@ struct ProcessorStorageConstructor {
{0xf000, 0x6000, Operation::Bcc, Decoder::Bcc_BSR}, // 4-25 (p129) and 4-59 (p163) {0xf000, 0x6000, Operation::Bcc, Decoder::Bcc_BSR}, // 4-25 (p129) and 4-59 (p163)
{0xf1c0, 0x41c0, Operation::MOVEAl, Decoder::LEA}, // 4-110 (p214) {0xf1c0, 0x41c0, Operation::MOVEAl, Decoder::LEA}, // 4-110 (p214)
{0xffc0, 0x4840, Operation::MOVEAl, Decoder::PEA}, // 4-159 (p263) {0xffc0, 0x4840, Operation::PEA, Decoder::PEA}, // 4-159 (p263)
{0xf100, 0x7000, Operation::MOVEq, Decoder::MOVEq}, // 4-134 (p238) {0xf100, 0x7000, Operation::MOVEq, Decoder::MOVEq}, // 4-134 (p238)
@ -803,7 +803,7 @@ struct ProcessorStorageConstructor {
bool is_byte_access = (op_mode&3) == 0; bool is_byte_access = (op_mode&3) == 0;
bool is_long_word_access = (op_mode&3) == 2; bool is_long_word_access = (op_mode&3) == 2;
// if(instruction == 0x206f) { // if(instruction == 0xbd50) {
// printf(""); // printf("");
// } // }
@ -993,7 +993,7 @@ struct ProcessorStorageConstructor {
case bw(Ind): // [AND/OR/EOR].bw Dn, (An) case bw(Ind): // [AND/OR/EOR].bw Dn, (An)
case bw(PostInc): // [AND/OR/EOR].bw Dn, (An)+ case bw(PostInc): // [AND/OR/EOR].bw Dn, (An)+
op(Action::None, seq("nr", { a(ea_register) }, !is_byte_access)); op(Action::None, seq("nrd", { a(ea_register) }, !is_byte_access));
op(Action::PerformOperation, seq("np nw", { a(ea_register) }, !is_byte_access)); op(Action::PerformOperation, seq("np nw", { a(ea_register) }, !is_byte_access));
if(mode == PostInc) { if(mode == PostInc) {
op(inc(ea_register) | MicroOp::DestinationMask); op(inc(ea_register) | MicroOp::DestinationMask);
@ -2388,8 +2388,7 @@ struct ProcessorStorageConstructor {
} break; } break;
case Decoder::PEA: { case Decoder::PEA: {
storage_.instructions[instruction].set_source(storage_, ea_mode, ea_register); storage_.instructions[instruction].set_source(storage_, An, ea_register);
storage_.instructions[instruction].destination = &storage_.destination_bus_data_[0]; storage_.instructions[instruction].destination = &storage_.destination_bus_data_[0];
storage_.instructions[instruction].destination_address = &storage_.address_[7]; storage_.instructions[instruction].destination_address = &storage_.address_[7];
@ -2401,13 +2400,13 @@ struct ProcessorStorageConstructor {
default: continue; default: continue;
case Ind: // PEA (An) case Ind: // PEA (An)
operation = Operation::MOVEAl;
op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask); op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask);
op(Action::PerformOperation, seq("np nW+ nw", { ea(1), ea(1) })); op(Action::PerformOperation, seq("np nW+ nw", { ea(1), ea(1) }));
break; break;
case XXXl: // PEA (XXX).l case XXXl: // PEA (XXX).l
case XXXw: // PEA (XXX).w case XXXw: // PEA (XXX).w
storage_.instructions[instruction].source = &storage_.effective_address_[0];
op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, (mode == XXXl) ? seq("np") : nullptr); op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask, (mode == XXXl) ? seq("np") : nullptr);
op(address_assemble_for_mode(mode) | MicroOp::SourceMask); op(address_assemble_for_mode(mode) | MicroOp::SourceMask);
op(Action::PerformOperation, seq("np nW+ nw np", { ea(1), ea(1) })); op(Action::PerformOperation, seq("np nW+ nw np", { ea(1), ea(1) }));
@ -2417,7 +2416,6 @@ struct ProcessorStorageConstructor {
case d16PC: // PEA (d16, PC) case d16PC: // PEA (d16, PC)
case d8AnXn: // PEA (d8, An, Xn) case d8AnXn: // PEA (d8, An, Xn)
case d8PCXn: // PEA (d8, PC, Xn) case d8PCXn: // PEA (d8, PC, Xn)
storage_.instructions[instruction].source = &storage_.effective_address_[0];
op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask); op(int(Action::CopyToEffectiveAddress) | MicroOp::DestinationMask);
op(calc_action_for_mode(mode) | MicroOp::SourceMask, seq(pseq("np", mode))); op(calc_action_for_mode(mode) | MicroOp::SourceMask, seq(pseq("np", mode)));
op(Action::PerformOperation, seq(pseq("np nW+ nw", mode), { ea(1), ea(1) })); op(Action::PerformOperation, seq(pseq("np nW+ nw", mode), { ea(1), ea(1) }));

1
Processors/68000/Implementation/68000Storage.hpp
View File

@ -92,6 +92,7 @@ class ProcessorStorage {
MOVEb, MOVEw, MOVEl, MOVEq, MOVEb, MOVEw, MOVEl, MOVEq,
MOVEAw, MOVEAl, MOVEAw, MOVEAl,
PEA,
MOVEtoSR, MOVEfromSR, MOVEtoSR, MOVEfromSR,
MOVEtoCCR, MOVEtoCCR,