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mirror of https://github.com/TomHarte/CLK.git synced 2024-11-26 23:52:26 +00:00

Teeters closer and closer to trying actually to run the Disk II state machine.

This commit is contained in:
Thomas Harte 2018-04-23 22:29:36 -07:00
parent 4bff44377a
commit 56d88f23ef
3 changed files with 50 additions and 9 deletions

View File

@ -18,20 +18,53 @@ void DiskII::set_control(Control control, bool on) {
void DiskII::set_mode(Mode mode) { void DiskII::set_mode(Mode mode) {
printf("Set mode %d\n", mode); printf("Set mode %d\n", mode);
state_ = (state_ & ~0x08) | ((mode == Mode::Write) ? 0x8 : 0x0);
} }
void DiskII::select_drive(int drive) { void DiskII::select_drive(int drive) {
printf("Select drive %d\n", drive); printf("Select drive %d\n", drive);
} }
void DiskII::set_shift_register(uint8_t value) { void DiskII::set_data_register(uint8_t value) {
printf("Set shift register\n"); printf("Set data register (?)\n");
state_ |= 0x4;
data_register_ = value;
} }
uint8_t DiskII::get_shift_register() { uint8_t DiskII::get_shift_register() {
printf("Get shift register\n"); printf("Get shift register (?)\n");
return 0xff; state_ &= ~0x4;
return shift_register_;
} }
void DiskII::run_for(const Cycles cycles) { void DiskII::run_for(const Cycles cycles) {
/*
... address the P6 ROM with an index byte built up as:
+-------+-------+-------+-------+-------+-------+-------+-------+
| STATE | STATE | STATE | PULSE | Q7 | Q6 | SR | STATE |
| bit 0 | bit 2 | bit 3 | | | | MSB | bit 1 |
+-------+-------+-------+-------+-------+-------+-------+-------+
7 6 5 4 3 2 1 0
...
The bytes in the P6 ROM has the high four bits reversed compared to the BAPD charts, so you will have to reverse them after fetching the byte.
*/
uint8_t command = 0;
switch(command) {
case 0x0: shift_register_ = 0; break; // clear
case 0x9: shift_register_ = static_cast<uint8_t>(shift_register_ << 1); break; // shift left, bringing in a zero
case 0xd: shift_register_ = static_cast<uint8_t>((shift_register_ << 1) | 1); break; // shift left, bringing in a one
case 0xa:
shift_register_ = (shift_register_ >> 1) | (is_write_protected() ? 0x80 : 0x00);
break; // shift right, bringing in write protected status
case 0xb: shift_register_ = data_register_; break; // load
default: break;
}
}
bool DiskII::is_write_protected() {
return true;
} }

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@ -29,10 +29,17 @@ class DiskII {
void set_control(Control control, bool on); void set_control(Control control, bool on);
void set_mode(Mode mode); void set_mode(Mode mode);
void select_drive(int drive); void select_drive(int drive);
void set_shift_register(uint8_t value); void set_data_register(uint8_t value);
uint8_t get_shift_register(); uint8_t get_shift_register();
void run_for(const Cycles cycles); void run_for(const Cycles cycles);
private:
uint8_t state_ = 0;
uint8_t shift_register_ = 0;
uint8_t data_register_ = 0;
bool is_write_protected();
}; };
} }

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@ -43,14 +43,15 @@ void DiskIICard::perform_bus_operation(CPU::MOS6502::BusOperation operation, uin
case 0xa: diskii_.select_drive(0); break; case 0xa: diskii_.select_drive(0); break;
case 0xb: diskii_.select_drive(1); break; case 0xb: diskii_.select_drive(1); break;
case 0xc: case 0xc: {
/* shift register? */ /* shift register? */
const uint8_t shift_value = diskii_.get_shift_register();
if(isReadOperation(operation)) if(isReadOperation(operation))
*value = diskii_.get_shift_register(); *value = shift_value;
break; } break;
case 0xd: case 0xd:
/* data register? */ /* data register? */
diskii_.set_shift_register(*value); diskii_.set_data_register(*value);
break; break;
case 0xe: diskii_.set_mode(Mode::Read); break; case 0xe: diskii_.set_mode(Mode::Read); break;