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https://github.com/TomHarte/CLK.git
synced 2025-04-09 15:39:08 +00:00
Continue failing. This is the story of my life.
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Thomas Harte
parent
11190cff1d
commit
56f271c8ad
@ -712,10 +712,9 @@ private:
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set_use_fast_tape();
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}
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void read_dipole() {
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if(pulse_num_ == 15225) {
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if(pulse_num_ >= 15225) {
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printf("");
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}
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// Provides an HLE implementation of the routine beginning at address
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// 0xe5fd in the ROM, i.e. rddipl (read dipole) as that's the one that
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// spins awaiting changes in tape input.
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@ -728,19 +727,24 @@ private:
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const unsigned int timer_clock_rate =
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static_cast<unsigned int>(get_clock_rate()) / video_.timer_cycle_length().as<unsigned int>();
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//; trigger on negative edge (beginning) of dipole
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//;
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//rddipl
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// ldx dsamp1 ; setup x,y with 1st sample point
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// ldy dsamp1+1
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//badeg1
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// lda dsamp2+1 ; put 2nd samp value on stack in reverse order
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// pha
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// lda dsamp2
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// pha
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const auto wait_for = [&](Pulse::Type type) -> bool {
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while(!tape_player_->is_at_end() && tape_player_->current_pulse().type != type) {
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tape_player_->complete_pulse();
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}
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return tape_player_->current_pulse().type == type;
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};
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const auto read16 = [&](uint16_t address) {
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return uint16_t( map_.read(address) | (map_.read(address + 1) << 8) );
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};
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const auto pulse_timer_cycles = [&] {
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const auto length = tape_player_->current_pulse().length;
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return (length.length * timer_clock_rate) / length.clock_rate;
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};
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//
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// Grab timing constants, and put one into memory as it had been on the stack.
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//
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const auto dsamp1 = read16(0x7b8);
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const auto dsamp2 = read16(0x7ba);
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const auto zcell = read16(0x7bc);
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@ -750,258 +754,57 @@ private:
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map_.write(0x100 + s) = uint8_t (dsamp2);
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//
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// lda #$10
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//rwtl ; wait till rd line is high
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// bit port
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// beq rwtl ; !ls!
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// Busy wait for high input from tape (Elaboration: exiting with error if the tape ends).
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//
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const auto wait_for = [&](Pulse::Type type) -> bool {
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while(!tape_player_->is_at_end() && tape_player_->current_pulse().type != type) {
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tape_player_->complete_pulse();
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}
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return tape_player_->current_pulse().type == type;
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};
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if(!wait_for(Pulse::Low)) {
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flags |= Flag::Carry;
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m6502_.set_value_of(Register::Flags, flags);
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return;
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}
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//
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//rwth ;it's high...now wait till it's low
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// bit port
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// bne rwth ; caught the edge
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// Busy wait for low input from tape (Elaboration: exiting with error if the tape ends).
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//
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if(!wait_for(Pulse::High)) {
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flags |= Flag::Carry;
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m6502_.set_value_of(Register::Flags, flags);
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return;
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}
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// stx timr2l
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// sty timr2h
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//
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//; go! ...ta
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// If tape input goes high before dsamp1 cycles, report a short.
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//
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// pla ;go! ...ta
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// sta timr3l
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// pla
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// sta timr3h ;go! ...tb
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//
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//; clear timer flags
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//
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// lda #$50 ; clr ta,tb
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// sta tedirq
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//
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//; um...check that edge again
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//
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//casdb1
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// lda port
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// cmp port
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// bne casdb1 ; something is going on here...
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// and #$10 ; a look at that edge again
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// bne badeg1 ; woa! got a bad edge trigger !ls!
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//
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//; must have been a valid edge
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//;
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//; do stop key check here
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//
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// jsr balout
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// lda #$10
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//wata ; wait for ta to timeout
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// bit port ; kuldge, kludge, kludge !!! <<><>>
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// bne rshort ; kuldge, kludge, kludge !!! <<><>>
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// bit tedirq
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// beq wata
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//
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//; now do the dipole sample #1
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//
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//casdb2
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// lda port
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// cmp port
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// bne casdb2
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// and #$10
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// bne rshort ; shorts anyone?
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//
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const auto pulse_timer_cycles = [&] {
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const auto length = tape_player_->current_pulse().length;
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return (length.length * timer_clock_rate) / length.clock_rate;
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};
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const auto pulse_length = pulse_timer_cycles();
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if(pulse_length <= dsamp1) {
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// Goto rshort, i.e. ...
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flags |= Flag::Overflow;
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flags &= ~Flag::Carry;
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m6502_.set_value_of(Register::Flags, flags);
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return;
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}
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if(pulse_length <= dsamp2) {
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//
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// Wait until end of dsamp1 period, then wait on until input is high, then wait until end of dsamp2 period.
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// If input is then low, it's a long.
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//
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tape_player_->complete_pulse();
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const auto second_pulse_length = pulse_timer_cycles();
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if(second_pulse_length + pulse_length <= dsamp2) {
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// Goto rlong, i.e. ...
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flags &= ~(Flag::Carry | Flag::Sign);
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m6502_.set_value_of(Register::Flags, flags);
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return;
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}
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// Test for a word by looking at the second part of the pulse.
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tape_player_->complete_pulse();
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const auto second_pulse_length = pulse_timer_cycles();
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if(second_pulse_length <= zcell) {
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//
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// Now wait an additional zcell clocks. If input is still low, that's an error. Otherwise it's a word.
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//
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if(second_pulse_length + pulse_length > dsamp2 + zcell) {
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flags |= Flag::Carry;
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} else {
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flags |= Flag::Sign;
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flags &= ~(Flag::Carry | Flag::Overflow);
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m6502_.set_value_of(Register::Flags, flags);
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return;
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}
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flags |= Flag::Carry;
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m6502_.set_value_of(Register::Flags, flags);
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//; perhaps a long or a word?
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//
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// lda #$40
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//watb
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// bit tedirq
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// beq watb
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//
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//; wait for tb to timeout
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//; now do the dipole sample #2
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//
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//casdb3
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// lda port
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// cmp port
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// bne casdb3
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// and #$10
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// bne rlong ; looks like a long from here !ls!
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// ; or could it be a word?
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// lda zcell
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// sta timr2l
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// lda zcell+1
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// sta timr2h
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// ; go! z-cell check
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// ; clear ta flag
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// lda #$10
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// sta tedirq ; verify +180 half of word dipole
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// lda #$10
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//wata2
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// bit tedirq
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// beq wata2 ; check z-cell is low
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//casdb4
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// lda port
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// cmp port
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// bne casdb4
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// and #$10
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// beq rderr1 ; !ls!
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// bit twordd ; got a word dipole
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// bmi dipok ; !bra
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//
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//rshort
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// bit tshrtd ; got a short
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// bvs dipok ; !bra
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//
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//rlong
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// bit tlongd ; got a long
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//
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//dipok
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// clc ; everything's fine
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// rts
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//
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//rderr1
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// sec ; i'm confused
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// rts
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// ++pulse_num;
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// const bool is_interesting = pulse_num >= 15220;
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//
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// if(pulse_num == 15224) {
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// printf("");
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// }
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//
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//// if(address == 0xe68a) {
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//// }
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//
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// if(address == 0xe5fd) {
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// // TODO:
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// //
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// // ; read a dipole from tape (and then RTS)
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// // ;
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// // ; if c=1 then error
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// // ; else if v=1 then short
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// // ; else if n=0 then long
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// // ; else word
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// // ; end
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// // ; end
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// // ; end
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//
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// // 76 = V, not N or C
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// // b7 = N
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//
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// // Compare with:
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// //
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// // dsamp1 *=*+2 ;time constant for x cell sample 07B8
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// // dsamp2 *=*+2 ;time constant for y cell sample
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// // zcell *=*+2 ;time constant for z cell verify
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//
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// const auto zcell = read16(0x7bc);
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// using Pulse = Storage::Tape::Pulse;
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//
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// // Wait until tape input is high (i.e. input is low).
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//// while(tape_player_->current_pulse().type != Pulse::Type::Low) {
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//// tape_player_->complete_pulse();
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//// }
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//
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// // Wait until tape input is low.
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// while(tape_player_->current_pulse().type != Pulse::Type::High) {
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// tape_player_->complete_pulse();
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// }
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//
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// // Count time of low high, and classify.
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// const auto length1 = tape_player_->current_pulse().length.get<float>();
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// tape_player_->complete_pulse(); // Consume High.
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// const auto length2 = tape_player_->current_pulse().length.get<float>();
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// tape_player_->complete_pulse(); // Consume Low.
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//
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// uint8_t flags =
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// uint8_t(m6502_.value_of(CPU::MOS6502::Register::Flags)) &
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// ~(CPU::MOS6502::Flag::Carry | CPU::MOS6502::Flag::Overflow | CPU::MOS6502::Flag::Sign);
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//
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// if(std::abs(length1 - length2) > 0.00025f) {
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// // Lengths are too dissimilar; call that an error.
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// flags |= CPU::MOS6502::Flag::Carry;
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// }
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//
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//// const auto dsamp1_difference = std::abs(length1 - dsamp1);
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//// const auto dsamp2_difference = std::abs(length1 - dsamp2);
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//// const auto zcell_difference = std::abs(length1 - zcell);
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//
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// if(length2 < dsamp1) {
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// flags |= CPU::MOS6502::Flag::Overflow;
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// } else if(length2 > zcell) {
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// flags |= CPU::MOS6502::Flag::Sign;
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// }
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//
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// m6502_.set_value_of(CPU::MOS6502::Register::Flags, flags);
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//
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// if(is_interesting) {
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// logger.info().append("Read: %d %d",
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// int(length1 * 1'000'000),
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// int(length2 * 1'000'000)
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// );
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// }
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//
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// *value = 0x60; // i.e. RTS.
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// }
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//
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// if(is_interesting) {
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// const auto flags = m6502_.value_of(CPU::MOS6502::Register::Flags);
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// logger.info().append("%d @ %d dipole result: %c%c%c",
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// pulse_num,
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// tape_player_->event_count(),
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// flags & CPU::MOS6502::Flag::Sign ? 'n' : '-',
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// flags & CPU::MOS6502::Flag::Overflow ? 'v' : '-',
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// flags & CPU::MOS6502::Flag::Carry ? 'c' : '-');
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//}
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// } else {
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}
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uint8_t io_direction_ = 0x00, io_output_ = 0x00;
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