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Corrects sampling of MREQ.

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This commit is contained in:
Thomas Harte 2021-04-08 19:21:35 -04:00
parent cd787486d2
commit 57a7e0834f
2 changed files with 5 additions and 3 deletions
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2
OSBindings/Mac/Clock SignalTests/Z80ContentionTests.mm
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@ -128,7 +128,7 @@ struct ContentionCheck {
if( if(
!count || // i.e. is at start. !count || // i.e. is at start.
(&record == &bus_records.back()) || // i.e. is at end. (&record == &bus_records.back()) || // i.e. is at end.
!(record.mreq || record.refresh) // i.e. beginning of a new contention. !record.mreq // i.e. beginning of a new contention.
) { ) {
if(count) { if(count) {
XCTAssertNotEqual(contention, contentions.end()); XCTAssertNotEqual(contention, contentions.end());

6
Processors/Z80/Z80.hpp
View File

@ -164,6 +164,8 @@ struct PartialMachineCycle {
/// @returns A C-style array of the bus state at the beginning of each half cycle in this /// @returns A C-style array of the bus state at the beginning of each half cycle in this
/// partial machine cycle. Each element is a combination of bit masks from the Line enum; /// partial machine cycle. Each element is a combination of bit masks from the Line enum;
/// bit set means line active, bit clear means line inactive. For the CLK line set means high. /// bit set means line active, bit clear means line inactive. For the CLK line set means high.
///
/// @discussion This discrete sampling is prone to aliasing errors. Beware.
const uint8_t *bus_state() const { const uint8_t *bus_state() const {
switch(operation) { switch(operation) {
@ -191,10 +193,10 @@ struct PartialMachineCycle {
case Operation::Refresh: { case Operation::Refresh: {
static constexpr uint8_t states[] = { static constexpr uint8_t states[] = {
Line::CLK | Line::RFSH,
Line::RFSH | Line::MREQ,
Line::CLK | Line::RFSH | Line::MREQ, Line::CLK | Line::RFSH | Line::MREQ,
Line::RFSH, Line::RFSH,
Line::CLK | Line::RFSH | Line::MREQ,
Line::RFSH | Line::MREQ,
Line::CLK | Line::RFSH, Line::CLK | Line::RFSH,
Line::RFSH, Line::RFSH,
}; };