From 57aa8d2f17139b65cc6bf0a0354aab42549f585e Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Sun, 29 May 2022 14:34:06 -0400
Subject: [PATCH] Correct timing of ADDQ.

---
 .../Implementation/68000Mk2Implementation.hpp | 29 ++++++++++++-------
 1 file changed, 18 insertions(+), 11 deletions(-)

diff --git a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
index e75ad731e..3577f79fa 100644
--- a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
+++ b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
@@ -747,18 +747,25 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
 				Duplicate(SUBb, ADDb)	StdCASE(ADDb,		perform_state_ = Perform_np)
 				Duplicate(SUBw, ADDw)	StdCASE(ADDw,		perform_state_ = Perform_np)
 				Duplicate(SUBl, ADDl)	StdCASE(ADDl, {
-					if(instruction_.mode(1) != Mode::DataRegisterDirect) {
-						perform_state_ = Perform_np;
+					if(instruction_.mode(0) == Mode::Quick) {
+						perform_state_ = (
+							instruction_.mode(1) == Mode::AddressRegisterDirect ||
+							instruction_.mode(1) == Mode::DataRegisterDirect
+						) ? Perform_np_nn : Perform_np;
 					} else {
-						switch(instruction_.mode(0)) {
-							default:
-								perform_state_ = Perform_np_n;
-							break;
-							case Mode::DataRegisterDirect:
-							case Mode::AddressRegisterDirect:
-							case Mode::ImmediateData:
-								perform_state_ = Perform_np_nn;
-							break;
+						if(instruction_.mode(1) != Mode::DataRegisterDirect) {
+							perform_state_ = Perform_np;
+						} else {
+							switch(instruction_.mode(0)) {
+								default:
+									perform_state_ = Perform_np_n;
+								break;
+								case Mode::DataRegisterDirect:
+								case Mode::AddressRegisterDirect:
+								case Mode::ImmediateData:
+									perform_state_ = Perform_np_nn;
+								break;
+							}
 						}
 					}
 				})