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Implements ANDI/ORI/EOR to SR/CCR.
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@ -482,7 +482,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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break;
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break;
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/*
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/*
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Status word moves.
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Status word moves and manipulations.
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*/
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*/
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case Operation::MOVEtoSR:
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case Operation::MOVEtoSR:
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@ -497,6 +497,35 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
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set_ccr(active_program_->source->full);
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set_ccr(active_program_->source->full);
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break;
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break;
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#define and_op(a, b) a &= b
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#define or_op(a, b) a |= b
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#define eor_op(a, b) a ^= b
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#define apply(op, func) {\
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auto status = get_status(); \
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op(status, prefetch_queue_.halves.high.full); \
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func(status); \
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program_counter_.full -= 2; \
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}
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#define apply_sr(op) apply(op, set_status)
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#define apply_ccr(op) apply(op, set_ccr)
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case Operation::ANDItoSR: apply_sr(and_op); break;
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case Operation::EORItoSR: apply_sr(eor_op); break;
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case Operation::ORItoSR: apply_sr(or_op); break;
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case Operation::ANDItoCCR: apply_ccr(and_op); break;
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case Operation::EORItoCCR: apply_ccr(eor_op); break;
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case Operation::ORItoCCR: apply_ccr(or_op); break;
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#undef apply_ccr
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#undef apply_sr
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#undef apply
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#undef eor_op
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#undef or_op
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#undef and_op
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/*
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/*
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Multiplications.
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Multiplications.
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*/
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*/
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@ -416,6 +416,8 @@ struct ProcessorStorageConstructor {
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EXG, // Maps source and destination registers and an operation mode to an EXG.
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EXG, // Maps source and destination registers and an operation mode to an EXG.
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SWAP, // Maps a source register to a SWAP.
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SWAP, // Maps a source register to a SWAP.
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EORI_ORI_ANDI_SR, // Maps to an EORI, ORI or ANDI to SR/CCR.
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};
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};
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using Operation = ProcessorStorage::Operation;
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using Operation = ProcessorStorage::Operation;
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@ -616,6 +618,13 @@ struct ProcessorStorageConstructor {
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{0xf1f8, 0xc188, Operation::EXG, Decoder::EXG}, // 4-105 (p209)
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{0xf1f8, 0xc188, Operation::EXG, Decoder::EXG}, // 4-105 (p209)
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{0xfff8, 0x4840, Operation::SWAP, Decoder::SWAP}, // 4-185 (p289)
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{0xfff8, 0x4840, Operation::SWAP, Decoder::SWAP}, // 4-185 (p289)
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{0xffff, 0x027c, Operation::ANDItoSR, Decoder::EORI_ORI_ANDI_SR},
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{0xffff, 0x023c, Operation::ANDItoCCR, Decoder::EORI_ORI_ANDI_SR},
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{0xffff, 0x0a7c, Operation::EORItoSR, Decoder::EORI_ORI_ANDI_SR},
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{0xffff, 0x0a3c, Operation::EORItoCCR, Decoder::EORI_ORI_ANDI_SR},
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{0xffff, 0x007c, Operation::ORItoSR, Decoder::EORI_ORI_ANDI_SR},
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{0xffff, 0x003c, Operation::ORItoCCR, Decoder::EORI_ORI_ANDI_SR},
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};
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};
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std::vector<size_t> micro_op_pointers(65536, std::numeric_limits<size_t>::max());
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std::vector<size_t> micro_op_pointers(65536, std::numeric_limits<size_t>::max());
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@ -661,6 +670,13 @@ struct ProcessorStorageConstructor {
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#define inc(n) increment_action(is_long_word_access, is_byte_access, n)
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#define inc(n) increment_action(is_long_word_access, is_byte_access, n)
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switch(mapping.decoder) {
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switch(mapping.decoder) {
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case Decoder::EORI_ORI_ANDI_SR: {
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// The source used here is always the high word of the prefetch queue.
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storage_.instructions[instruction].requires_supervisor = !(instruction & 0x40);
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op(Action::None, seq("np nn nn"));
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op(Action::PerformOperation, seq("np np"));
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} break;
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case Decoder::SWAP: {
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case Decoder::SWAP: {
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storage_.instructions[instruction].set_destination(storage_, Dn, ea_register);
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storage_.instructions[instruction].set_destination(storage_, Dn, ea_register);
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op(Action::PerformOperation, seq("np"));
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op(Action::PerformOperation, seq("np"));
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@ -62,6 +62,10 @@ class ProcessorStorage {
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MOVEtoSR, MOVEfromSR,
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MOVEtoSR, MOVEfromSR,
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MOVEtoCCR,
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MOVEtoCCR,
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ORItoSR, ORItoCCR,
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ANDItoSR, ANDItoCCR,
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EORItoSR, EORItoCCR,
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BTSTb, BTSTl,
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BTSTb, BTSTl,
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BCLRl, BCLRb,
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BCLRl, BCLRb,
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CMPb, CMPw, CMPl,
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CMPb, CMPw, CMPl,
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