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Starts accumulating disk data.
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@ -533,7 +533,7 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
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cycle.set_value16(0xff00);
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break;
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// Disk DMA.
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// Disk DMA and control.
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case Write(0x020): disk_.set_pointer<0, 16>(cycle.value16()); break;
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case Write(0x022): disk_.set_pointer<0, 0>(cycle.value16()); break;
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case Write(0x024): disk_.set_length(cycle.value16()); break;
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@ -542,6 +542,23 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
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LOG("TODO: disk DMA; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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break;
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case Write(0x09e):
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ApplySetClear(paula_disk_control_);
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disk_controller_.set_control(paula_disk_control_);
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// TODO: should also post to Paula.
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break;
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case Read(0x010):
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cycle.set_value16(paula_disk_control_);
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break;
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case Write(0x07e):
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disk_controller_.set_sync_word(cycle.value16());
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break;
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case Read(0x01a):
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LOG("TODO: disk status");
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break;
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// Refresh.
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case Write(0x028):
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LOG("TODO (maybe): refresh; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
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@ -694,7 +711,6 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
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case Write(0x074): blitter_.set_data(0, cycle.value16()); break;
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// Paula.
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case Write(0x09e):
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case Write(0x0a0): case Write(0x0a2): case Write(0x0a4): case Write(0x0a6):
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case Write(0x0a8): case Write(0x0aa):
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case Write(0x0b0): case Write(0x0b2): case Write(0x0b4): case Write(0x0b6):
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@ -1024,8 +1040,33 @@ Chipset::DiskController::DiskController(Cycles clock_rate) :
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}
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void Chipset::DiskController::process_input_bit(int value) {
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// TODO:
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(void)value;
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data_ = uint16_t((data_ << 1) | value);
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++bit_count_;
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// if(!(bit_count_&15)) {
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// LOG("Word: " << PADHEX(4) << data_);
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// }
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}
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void Chipset::DiskController::set_sync_word(uint16_t value) {
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sync_word_ = value;
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}
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void Chipset::DiskController::set_control(uint16_t control) {
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// b13 and b14: precompensation length specifier
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// b12: 0 => GCR precompensation; 1 => MFM.
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// b10: 1 => enable use of word sync; 0 => disable.
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// b9: 1 => sync on MSB (Disk II style, presumably?); 0 => don't.
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// b8: 1 => 2µs per bit; 0 => 4µs.
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sync_with_word_ = control & 0x400;
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Storage::Time bit_length;
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bit_length.length = 1;
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bit_length.clock_rate = (control & 0x100) ? 500000 : 250000;
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set_expected_bit_length(bit_length);
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LOG((sync_with_word_ ? "Will" : "Won't") << " sync with word; bit length is " << ((control & 0x100) ? "short" : "long"));
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}
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void Chipset::DiskController::process_index_hole() {
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@ -238,6 +238,9 @@ class Chipset: private ClockingHint::Observer {
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bool insert(const std::shared_ptr<Storage::Disk::Disk> &disk, size_t drive);
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void set_activity_observer(Activity::Observer *);
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void set_sync_word(uint16_t);
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void set_control(uint16_t);
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private:
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void process_input_bit(int value) final;
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void process_index_hole() final;
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@ -247,9 +250,16 @@ class Chipset: private ClockingHint::Observer {
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uint32_t drive_ids_[4]{};
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uint32_t previous_select_ = 0;
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uint16_t data_ = 0;
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int bit_count_ = 0;
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uint16_t sync_word_ = 0;
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bool sync_with_word_ = false;
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} disk_controller_;
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void set_component_prefers_clocking(ClockingHint::Source *, ClockingHint::Preference) final;
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bool disk_controller_is_sleeping_ = false;
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uint16_t paula_disk_control_ = 0;
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class DiskDMA: public DMADevice<1> {
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public:
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