6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2025-01-27 06:35:04 +00:00
Code Issues Projects Releases Wiki Activity

Starts accumulating disk data.

Browse Source
This commit is contained in:
Thomas Harte 2021-10-07 05:11:32 -07:00
parent ed303310bb
commit 5899af0038
2 changed files with 55 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

49
Machines/Amiga/Chipset.cpp
View File

@ -533,7 +533,7 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
cycle.set_value16(0xff00); cycle.set_value16(0xff00);
break; break;
// Disk DMA. // Disk DMA and control.
case Write(0x020): disk_.set_pointer<0, 16>(cycle.value16()); break; case Write(0x020): disk_.set_pointer<0, 16>(cycle.value16()); break;
case Write(0x022): disk_.set_pointer<0, 0>(cycle.value16()); break; case Write(0x022): disk_.set_pointer<0, 0>(cycle.value16()); break;
case Write(0x024): disk_.set_length(cycle.value16()); break; case Write(0x024): disk_.set_length(cycle.value16()); break;
@ -542,6 +542,23 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
LOG("TODO: disk DMA; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address); LOG("TODO: disk DMA; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
break; break;
case Write(0x09e):
ApplySetClear(paula_disk_control_);
disk_controller_.set_control(paula_disk_control_);
// TODO: should also post to Paula.
break;
case Read(0x010):
cycle.set_value16(paula_disk_control_);
break;
case Write(0x07e):
disk_controller_.set_sync_word(cycle.value16());
break;
case Read(0x01a):
LOG("TODO: disk status");
break;
// Refresh. // Refresh.
case Write(0x028): case Write(0x028):
LOG("TODO (maybe): refresh; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address); LOG("TODO (maybe): refresh; " << PADHEX(4) << cycle.value16() << " to " << *cycle.address);
@ -694,7 +711,6 @@ void Chipset::perform(const CPU::MC68000::Microcycle &cycle) {
case Write(0x074): blitter_.set_data(0, cycle.value16()); break; case Write(0x074): blitter_.set_data(0, cycle.value16()); break;
// Paula. // Paula.
case Write(0x09e):
case Write(0x0a0): case Write(0x0a2): case Write(0x0a4): case Write(0x0a6): case Write(0x0a0): case Write(0x0a2): case Write(0x0a4): case Write(0x0a6):
case Write(0x0a8): case Write(0x0aa): case Write(0x0a8): case Write(0x0aa):
case Write(0x0b0): case Write(0x0b2): case Write(0x0b4): case Write(0x0b6): case Write(0x0b0): case Write(0x0b2): case Write(0x0b4): case Write(0x0b6):
@ -1024,8 +1040,33 @@ Chipset::DiskController::DiskController(Cycles clock_rate) :
} }
void Chipset::DiskController::process_input_bit(int value) { void Chipset::DiskController::process_input_bit(int value) {
// TODO: data_ = uint16_t((data_ << 1) | value);
(void)value; ++bit_count_;
// if(!(bit_count_&15)) {
// LOG("Word: " << PADHEX(4) << data_);
// }
}
void Chipset::DiskController::set_sync_word(uint16_t value) {
sync_word_ = value;
}
void Chipset::DiskController::set_control(uint16_t control) {
// b13 and b14: precompensation length specifier
// b12: 0 => GCR precompensation; 1 => MFM.
// b10: 1 => enable use of word sync; 0 => disable.
// b9: 1 => sync on MSB (Disk II style, presumably?); 0 => don't.
// b8: 1 => 2µs per bit; 0 => 4µs.
sync_with_word_ = control & 0x400;
Storage::Time bit_length;
bit_length.length = 1;
bit_length.clock_rate = (control & 0x100) ? 500000 : 250000;
set_expected_bit_length(bit_length);
LOG((sync_with_word_ ? "Will" : "Won't") << " sync with word; bit length is " << ((control & 0x100) ? "short" : "long"));
} }
void Chipset::DiskController::process_index_hole() { void Chipset::DiskController::process_index_hole() {

10
Machines/Amiga/Chipset.hpp
View File

@ -238,6 +238,9 @@ class Chipset: private ClockingHint::Observer {
bool insert(const std::shared_ptr<Storage::Disk::Disk> &disk, size_t drive); bool insert(const std::shared_ptr<Storage::Disk::Disk> &disk, size_t drive);
void set_activity_observer(Activity::Observer *); void set_activity_observer(Activity::Observer *);
void set_sync_word(uint16_t);
void set_control(uint16_t);
private: private:
void process_input_bit(int value) final; void process_input_bit(int value) final;
void process_index_hole() final; void process_index_hole() final;
@ -247,9 +250,16 @@ class Chipset: private ClockingHint::Observer {
uint32_t drive_ids_[4]{}; uint32_t drive_ids_[4]{};
uint32_t previous_select_ = 0; uint32_t previous_select_ = 0;
uint16_t data_ = 0;
int bit_count_ = 0;
uint16_t sync_word_ = 0;
bool sync_with_word_ = false;
} disk_controller_; } disk_controller_;
void set_component_prefers_clocking(ClockingHint::Source *, ClockingHint::Preference) final; void set_component_prefers_clocking(ClockingHint::Source *, ClockingHint::Preference) final;
bool disk_controller_is_sleeping_ = false; bool disk_controller_is_sleeping_ = false;
uint16_t paula_disk_control_ = 0;
class DiskDMA: public DMADevice<1> { class DiskDMA: public DMADevice<1> {
public: public: