mirror of
https://github.com/TomHarte/CLK.git
synced 2025-01-11 08:30:55 +00:00
Moves the CIAs into the Chipset class.
This reflects the routing of interrupt signals for now, but also prepares for the addition of disk drives.
This commit is contained in:
Thomas Harte
parent
da286d5ae8
commit
5ccb512883
@ -13,18 +13,19 @@
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#include "../../Processors/68000/68000.hpp"
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#include "../../Components/6526/6526.hpp"
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#include "../../Analyser/Static/Amiga/Target.hpp"
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#include "../Utility/MemoryPacker.hpp"
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#include "../Utility/MemoryFuzzer.hpp"
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#include "../../Storage/Disk/Drive.hpp"
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//#define NDEBUG
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#define LOG_PREFIX "[Amiga] "
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#include "../../Outputs/Log.hpp"
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#include "Chipset.hpp"
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#include "MemoryMap.hpp"
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namespace Amiga {
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@ -37,10 +38,7 @@ class ConcreteMachine:
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public:
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ConcreteMachine(const Analyser::Static::Amiga::Target &target, const ROMMachine::ROMFetcher &rom_fetcher) :
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mc68000_(*this),
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chipset_(reinterpret_cast<uint16_t *>(memory_.chip_ram.data()), memory_.chip_ram.size() >> 1),
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cia_a_handler_(memory_),
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cia_a_(cia_a_handler_),
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cia_b_(cia_b_handler_)
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chipset_(memory_)
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{
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(void)target;
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@ -61,40 +59,17 @@ class ConcreteMachine:
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// MARK: - MC68000::BusHandler.
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using Microcycle = CPU::MC68000::Microcycle;
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HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int) {
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//
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// TODO: clean up below.
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//
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// Probably: let the Chipset own the CIAs, killing the need to pass hsyncs/vsyncs
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// and CIA interrupt lines back and forth. Then the two run_fors can return, at most,
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// an interrupt level and a duration. Possibly give the chipset a reference to the
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// 68k so it can set IPL directly?
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// Do a quick advance check for Chip RAM access; add a suitable delay if required.
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Chipset::Changes net_changes;
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HalfCycles access_delay;
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if(cycle.operation & Microcycle::NewAddress && *cycle.address < 0x20'0000) {
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// TODO: shouldn't delay if the overlay bit is set?
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net_changes = chipset_.run_until_cpu_slot();
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access_delay = net_changes.duration;
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access_delay = chipset_.run_until_cpu_slot().duration;
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}
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// Compute total length.
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const HalfCycles total_length = cycle.length + access_delay;
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// The CIAs are on the E clock.
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cia_divider_ += total_length;
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const HalfCycles e_clocks = cia_divider_.divide(HalfCycles(20));
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if(e_clocks > HalfCycles(0)) {
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cia_a_.run_for(e_clocks);
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cia_b_.run_for(e_clocks);
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}
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net_changes += chipset_.run_for(total_length);
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cia_a_.advance_tod(net_changes.vsyncs);
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cia_b_.advance_tod(net_changes.hsyncs);
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chipset_.set_cia_interrupts(cia_a_.get_interrupt_line(), cia_b_.get_interrupt_line());
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chipset_.run_for(total_length);
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mc68000_.set_interrupt_level(chipset_.get_interrupt_level());
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// Check for assertion of reset.
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@ -139,12 +114,12 @@ class ConcreteMachine:
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if(cycle.operation & Microcycle::Read) {
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uint16_t result = 0xffff;
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if(!(address & 0x1000)) result &= 0xff00 | (cia_a_.read(reg) << 0);
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if(!(address & 0x2000)) result &= 0x00ff | (cia_b_.read(reg) << 8);
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if(!(address & 0x1000)) result &= 0xff00 | (chipset_.cia_a.read(reg) << 0);
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if(!(address & 0x2000)) result &= 0x00ff | (chipset_.cia_b.read(reg) << 8);
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cycle.set_value16(result);
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} else {
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if(!(address & 0x1000)) cia_a_.write(reg, cycle.value8_low());
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if(!(address & 0x2000)) cia_b_.write(reg, cycle.value8_high());
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if(!(address & 0x1000)) chipset_.cia_a.write(reg, cycle.value8_low());
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if(!(address & 0x2000)) chipset_.cia_b.write(reg, cycle.value8_high());
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}
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LOG("CIA " << (((address >> 12) & 3)^3) << " " << (cycle.operation & Microcycle::Read ? "read " : "write ") << std::dec << (reg & 0xf) << " of " << PADHEX(2) << +cycle.value8_low());
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@ -168,33 +143,6 @@ class ConcreteMachine:
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&memory_.regions[address >> 18].contents[address],
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memory_.regions[address >> 18].read_write_mask
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);
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// if(address < 0x4'0000) {
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// switch((cycle.operation | memory_.regions[address >> 18].read_write_mask) & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read | Microcycle::PermitRead | Microcycle::PermitWrite)) {
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// default:
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// if(cycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte)) {
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// printf("Ignored!\n");
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// }
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// break;
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//
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// case Microcycle::SelectWord | Microcycle::Read | Microcycle::PermitRead:
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// case Microcycle::SelectWord | Microcycle::Read | Microcycle::PermitRead | Microcycle::PermitWrite:
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// printf("%04x -> %04x\n", *cycle.address, cycle.value->full);
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// break;
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// case Microcycle::SelectByte | Microcycle::Read | Microcycle::PermitRead:
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// case Microcycle::SelectByte | Microcycle::Read | Microcycle::PermitRead | Microcycle::PermitWrite:
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// printf("%04x -> %02x\n", *cycle.address, cycle.value->halves.low);
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// break;
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// case Microcycle::SelectWord | Microcycle::PermitWrite:
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// case Microcycle::SelectWord | Microcycle::PermitWrite | Microcycle::PermitRead:
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// printf("%04x <- %04x\n", *cycle.address, cycle.value->full);
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// break;
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// case Microcycle::SelectByte | Microcycle::PermitWrite:
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// case Microcycle::SelectByte | Microcycle::PermitWrite | Microcycle::PermitRead:
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// printf("%04x <- %02x\n", *cycle.address, cycle.value->halves.low);
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// break;
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// }
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// }
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}
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return access_delay;
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@ -204,172 +152,16 @@ class ConcreteMachine:
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CPU::MC68000::Processor<ConcreteMachine, true> mc68000_;
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// MARK: - Memory map.
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struct MemoryMap {
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public:
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std::array<uint8_t, 512*1024> chip_ram{};
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std::array<uint8_t, 512*1024> kickstart{0xff};
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struct MemoryRegion {
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uint8_t *contents = nullptr;
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unsigned int read_write_mask = 0;
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} regions[64]; // i.e. top six bits are used as an index.
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MemoryMap() {
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// Address spaces that matter:
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//
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// 00'0000 – 08'0000: chip RAM. [or overlayed KickStart]
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// – 10'0000: extended chip ram for ECS.
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// – 20'0000: auto-config space (/fast RAM).
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// ...
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// bf'd000 – c0'0000: 8250s.
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// c0'0000 – d8'0000: pseudo-fast RAM.
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// ...
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// dc'0000 – dd'0000: optional real-time clock.
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// df'f000 - e0'0000: custom chip registers.
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// ...
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// f0'0000 — : 512kb Kickstart (or possibly just an extra 512kb reserved for hypothetical 1mb Kickstart?).
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// f8'0000 — : 256kb Kickstart if 2.04 or higher.
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// fc'0000 – : 256kb Kickstart otherwise.
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set_region(0xfc'0000, 0x1'00'0000, kickstart.data(), CPU::MC68000::Microcycle::PermitRead);
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reset();
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}
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void reset() {
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set_overlay(true);
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}
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void set_overlay(bool enabled) {
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if(overlay_ == enabled) {
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return;
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}
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overlay_ = enabled;
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if(enabled) {
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set_region(0x00'0000, 0x08'0000, kickstart.data(), CPU::MC68000::Microcycle::PermitRead);
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} else {
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// Mirror RAM to fill out the address range up to $20'0000.
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set_region(0x00'0000, 0x08'0000, chip_ram.data(), CPU::MC68000::Microcycle::PermitRead | CPU::MC68000::Microcycle::PermitWrite);
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set_region(0x08'0000, 0x10'0000, chip_ram.data(), CPU::MC68000::Microcycle::PermitRead | CPU::MC68000::Microcycle::PermitWrite);
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set_region(0x10'0000, 0x18'0000, chip_ram.data(), CPU::MC68000::Microcycle::PermitRead | CPU::MC68000::Microcycle::PermitWrite);
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set_region(0x18'0000, 0x20'0000, chip_ram.data(), CPU::MC68000::Microcycle::PermitRead | CPU::MC68000::Microcycle::PermitWrite);
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}
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}
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private:
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bool overlay_ = false;
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void set_region(int start, int end, uint8_t *base, unsigned int read_write_mask) {
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assert(!(start & ~0xfc'0000));
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assert(!((end - (1 << 18)) & ~0xfc'0000));
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base -= start;
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for(int c = start >> 18; c < end >> 18; c++) {
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regions[c].contents = base;
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regions[c].read_write_mask = read_write_mask;
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}
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}
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} memory_;
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MemoryMap memory_;
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// MARK: - Chipset.
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Chipset chipset_;
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// MARK: - CIAs.
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class CIAAHandler: public MOS::MOS6526::PortHandler {
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public:
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CIAAHandler(MemoryMap &map) : map_(map) {}
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void set_port_output(MOS::MOS6526::Port port, uint8_t value) {
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if(port) {
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// Parallel port output.
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LOG("TODO: parallel output " << PADHEX(2) << +value);
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} else {
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// b7: /FIR1
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// b6: /FIR0
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// b5: /RDY
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// b4: /TRK0
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// b3: /WPRO
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// b2: /CHNG
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// b1: /LED [output]
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// b0: OVL [output]
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LOG("LED & memory map: " << PADHEX(2) << +value);
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if(observer_) {
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observer_->set_led_status(led_name, !(value & 2));
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}
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map_.set_overlay(value & 1);
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}
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}
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uint8_t get_port_input(MOS::MOS6526::Port port) {
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if(port) {
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LOG("TODO: parallel input?");
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} else {
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LOG("TODO: CIA A, port A input — FIR, RDY, TRK0, etc");
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// Announce that TRK0 is upon us.
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return 0xef;
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}
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return 0xff;
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}
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void set_activity_observer(Activity::Observer *observer) {
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observer_ = observer;
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if(observer) {
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observer->register_led(led_name, Activity::Observer::LEDPresentation::Persistent);
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}
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}
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private:
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MemoryMap &map_;
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Activity::Observer *observer_ = nullptr;
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inline static const std::string led_name = "Power";
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} cia_a_handler_;
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struct CIABHandler: public MOS::MOS6526::PortHandler {
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void set_port_output(MOS::MOS6526::Port port, uint8_t value) {
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if(port) {
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// Serial port control.
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//
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// b7: /DTR
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// b6: /RTS
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// b5: /CD
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// b4: /CTS
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// b3: /DSR
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// b2: SEL
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// b1: POUT
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// b0: BUSY
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LOG("TODO: DTR/RTS/etc: " << PADHEX(2) << +value);
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} else {
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// Disk motor control, drive and head selection,
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// and stepper control:
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//
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// b7: /MTR
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// b6: /SEL3
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// b5: /SEL2
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// b4: /SEL1
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// b3: /SEL0
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// b2: /SIDE
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// b1: DIR
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// b0: /STEP
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LOG("TODO: Stepping, etc; " << PADHEX(2) << +value);
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}
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}
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uint8_t get_port_input(MOS::MOS6526::Port) {
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LOG("Unexpected input for CIA B ");
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return 0xff;
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}
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} cia_b_handler_;
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HalfCycles cia_divider_;
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MOS::MOS6526::MOS6526<CIAAHandler, MOS::MOS6526::Personality::P8250> cia_a_;
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MOS::MOS6526::MOS6526<CIABHandler, MOS::MOS6526::Personality::P8250> cia_b_;
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// MARK: - Activity Source
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void set_activity_observer(Activity::Observer *observer) final {
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cia_a_handler_.set_activity_observer(observer);
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chipset_.set_activity_observer(observer);
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}
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// MARK: - MachineTypes::ScanProducer.
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@ -32,11 +32,14 @@ template <DMAFlag... Flags> struct DMAMask: Mask<DMAFlag, Flags...> {};
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}
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Chipset::Chipset(uint16_t *ram, size_t word_size) :
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blitter_(*this, ram, word_size),
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bitplanes_(*this, ram, word_size),
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copper_(*this, ram, word_size),
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disk_(*this, ram, word_size),
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Chipset::Chipset(MemoryMap &map) :
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cia_a_handler_(map),
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cia_a(cia_a_handler_),
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cia_b(cia_b_handler_),
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blitter_(*this, reinterpret_cast<uint16_t *>(map.chip_ram.data()), map.chip_ram.size() >> 1),
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bitplanes_(*this, reinterpret_cast<uint16_t *>(map.chip_ram.data()), map.chip_ram.size() >> 1),
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copper_(*this, reinterpret_cast<uint16_t *>(map.chip_ram.data()), map.chip_ram.size() >> 1),
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disk_(*this, reinterpret_cast<uint16_t *>(map.chip_ram.data()), map.chip_ram.size() >> 1),
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crt_(908, 4, Outputs::Display::Type::PAL50, Outputs::Display::InputDataType::Red4Green4Blue4) {
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}
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@ -48,12 +51,12 @@ Chipset::Changes Chipset::run_until_cpu_slot() {
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return run<true>();
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}
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void Chipset::set_cia_interrupts(bool cia_a, bool cia_b) {
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void Chipset::set_cia_interrupts(bool cia_a_interrupt, bool cia_b_interrupt) {
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// TODO: are these really latched, or are they active live?
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interrupt_requests_ &= ~InterruptMask<InterruptFlag::IOPortsAndTimers, InterruptFlag::External>::value;
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interrupt_requests_ |=
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(cia_a ? InterruptMask<InterruptFlag::IOPortsAndTimers>::value : 0) |
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(cia_b ? InterruptMask<InterruptFlag::External>::value : 0);
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(cia_a_interrupt ? InterruptMask<InterruptFlag::IOPortsAndTimers>::value : 0) |
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(cia_b_interrupt ? InterruptMask<InterruptFlag::External>::value : 0);
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update_interrupts();
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}
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@ -339,6 +342,7 @@ template <bool stop_on_cpu> Chipset::Changes Chipset::run(HalfCycles length) {
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// This code uses 'pixels' as a measure, which is equivalent to one pixel clock time,
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// or half a cycle.
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auto pixels_remaining = length.as<int>();
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int hsyncs = 0, vsyncs = 0;
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// Update raster position, spooling out graphics.
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while(pixels_remaining) {
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@ -369,7 +373,7 @@ template <bool stop_on_cpu> Chipset::Changes Chipset::run(HalfCycles length) {
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// Advance intraline counter and pcoossibly ripple upwards into
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// lines and fields.
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if(line_cycle_ == (line_length_ * 4)) {
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++changes.hsyncs;
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++hsyncs;
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line_cycle_ = 0;
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++y_;
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@ -385,7 +389,7 @@ template <bool stop_on_cpu> Chipset::Changes Chipset::run(HalfCycles length) {
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}
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if(y_ == frame_height_) {
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++changes.vsyncs;
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++vsyncs;
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interrupt_requests_ |= InterruptMask<InterruptFlag::VerticalBlank>::value;
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update_interrupts();
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@ -398,6 +402,18 @@ template <bool stop_on_cpu> Chipset::Changes Chipset::run(HalfCycles length) {
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assert(line_cycle_ < line_length_ * 4);
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}
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// The CIAs are on the E clock.
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cia_divider_ += changes.duration;
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const HalfCycles e_clocks = cia_divider_.divide(HalfCycles(20));
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if(e_clocks > HalfCycles(0)) {
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cia_a.run_for(e_clocks);
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cia_b.run_for(e_clocks);
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}
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cia_a.advance_tod(vsyncs);
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cia_b.advance_tod(hsyncs);
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set_cia_interrupts(cia_a.get_interrupt_line(), cia_b.get_interrupt_line());
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changes.interrupt_level = interrupt_level_;
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return changes;
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}
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@ -897,3 +913,82 @@ void Chipset::set_display_type(Outputs::Display::DisplayType type) {
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Outputs::Display::DisplayType Chipset::get_display_type() const {
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return crt_.get_display_type();
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}
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// MARK: - CIA Handlers.
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Chipset::CIAAHandler::CIAAHandler(MemoryMap &map) : map_(map) {}
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void Chipset::CIAAHandler::set_port_output(MOS::MOS6526::Port port, uint8_t value) {
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if(port) {
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// Parallel port output.
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LOG("TODO: parallel output " << PADHEX(2) << +value);
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} else {
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// b7: /FIR1
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// b6: /FIR0
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// b5: /RDY
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// b4: /TRK0
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// b3: /WPRO
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// b2: /CHNG
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// b1: /LED [output]
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// b0: OVL [output]
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LOG("LED & memory map: " << PADHEX(2) << +value);
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if(observer_) {
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observer_->set_led_status(led_name, !(value & 2));
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}
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map_.set_overlay(value & 1);
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}
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}
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uint8_t Chipset::CIAAHandler::get_port_input(MOS::MOS6526::Port port) {
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if(port) {
|
||||
LOG("TODO: parallel input?");
|
||||
} else {
|
||||
LOG("TODO: CIA A, port A input — FIR, RDY, TRK0, etc");
|
||||
|
||||
// Announce that TRK0 is upon us.
|
||||
return 0xef;
|
||||
}
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
void Chipset::CIAAHandler::set_activity_observer(Activity::Observer *observer) {
|
||||
observer_ = observer;
|
||||
if(observer) {
|
||||
observer->register_led(led_name, Activity::Observer::LEDPresentation::Persistent);
|
||||
}
|
||||
}
|
||||
|
||||
void Chipset::CIABHandler::set_port_output(MOS::MOS6526::Port port, uint8_t value) {
|
||||
if(port) {
|
||||
// Serial port control.
|
||||
//
|
||||
// b7: /DTR
|
||||
// b6: /RTS
|
||||
// b5: /CD
|
||||
// b4: /CTS
|
||||
// b3: /DSR
|
||||
// b2: SEL
|
||||
// b1: POUT
|
||||
// b0: BUSY
|
||||
LOG("TODO: DTR/RTS/etc: " << PADHEX(2) << +value);
|
||||
} else {
|
||||
// Disk motor control, drive and head selection,
|
||||
// and stepper control:
|
||||
//
|
||||
// b7: /MTR
|
||||
// b6: /SEL3
|
||||
// b5: /SEL2
|
||||
// b4: /SEL1
|
||||
// b3: /SEL0
|
||||
// b2: /SIDE
|
||||
// b1: DIR
|
||||
// b0: /STEP
|
||||
LOG("TODO: Stepping, etc; " << PADHEX(2) << +value);
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t Chipset::CIABHandler::get_port_input(MOS::MOS6526::Port) {
|
||||
LOG("Unexpected input for CIA B ");
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
@ -12,12 +12,15 @@
|
||||
#include <cstddef>
|
||||
#include <cstdint>
|
||||
|
||||
#include "../../Processors/68000/68000.hpp"
|
||||
#include "../../Activity/Source.hpp"
|
||||
#include "../../Components/6526/6526.hpp"
|
||||
#include "../../Outputs/CRT/CRT.hpp"
|
||||
#include "../../Processors/68000/68000.hpp"
|
||||
|
||||
#include "Blitter.hpp"
|
||||
#include "Copper.hpp"
|
||||
#include "DMADevice.hpp"
|
||||
#include "MemoryMap.hpp"
|
||||
|
||||
namespace Amiga {
|
||||
|
||||
@ -56,17 +59,13 @@ enum class DMAFlag: uint16_t {
|
||||
|
||||
class Chipset {
|
||||
public:
|
||||
Chipset(uint16_t *ram, size_t word_size);
|
||||
Chipset(MemoryMap &memory_map);
|
||||
|
||||
struct Changes {
|
||||
int hsyncs = 0;
|
||||
int vsyncs = 0;
|
||||
int interrupt_level = 0;
|
||||
HalfCycles duration;
|
||||
|
||||
Changes &operator += (const Changes &rhs) {
|
||||
hsyncs += rhs.hsyncs;
|
||||
vsyncs += rhs.vsyncs;
|
||||
duration += rhs.duration;
|
||||
return *this;
|
||||
}
|
||||
@ -95,9 +94,43 @@ class Chipset {
|
||||
void set_display_type(Outputs::Display::DisplayType);
|
||||
Outputs::Display::DisplayType get_display_type() const;
|
||||
|
||||
// Activity observation.
|
||||
void set_activity_observer(Activity::Observer *observer) {
|
||||
cia_a_handler_.set_activity_observer(observer);
|
||||
}
|
||||
|
||||
private:
|
||||
class CIAAHandler: public MOS::MOS6526::PortHandler {
|
||||
public:
|
||||
CIAAHandler(MemoryMap &map);
|
||||
void set_port_output(MOS::MOS6526::Port port, uint8_t value);
|
||||
uint8_t get_port_input(MOS::MOS6526::Port port);
|
||||
void set_activity_observer(Activity::Observer *observer);
|
||||
|
||||
private:
|
||||
MemoryMap &map_;
|
||||
Activity::Observer *observer_ = nullptr;
|
||||
inline static const std::string led_name = "Power";
|
||||
} cia_a_handler_;
|
||||
|
||||
struct CIABHandler: public MOS::MOS6526::PortHandler {
|
||||
void set_port_output(MOS::MOS6526::Port port, uint8_t value);
|
||||
uint8_t get_port_input(MOS::MOS6526::Port);
|
||||
} cia_b_handler_;
|
||||
|
||||
public:
|
||||
// CIAs are provided for direct access; it's up to the caller properly
|
||||
// to distinguish relevant accesses.
|
||||
MOS::MOS6526::MOS6526<CIAAHandler, MOS::MOS6526::Personality::P8250> cia_a;
|
||||
MOS::MOS6526::MOS6526<CIABHandler, MOS::MOS6526::Personality::P8250> cia_b;
|
||||
|
||||
private:
|
||||
friend class DMADeviceBase;
|
||||
|
||||
// MARK: - E Clock follow along.
|
||||
|
||||
HalfCycles cia_divider_;
|
||||
|
||||
// MARK: - Interrupts.
|
||||
|
||||
uint16_t interrupt_enable_ = 0;
|
||||
|
||||
81
Machines/Amiga/MemoryMap.hpp
Normal file
81
Machines/Amiga/MemoryMap.hpp
Normal file
@ -0,0 +1,81 @@
|
||||
//
|
||||
// MemoryMap.hpp
|
||||
// Clock Signal
|
||||
//
|
||||
// Created by Thomas Harte on 04/10/2021.
|
||||
// Copyright © 2021 Thomas Harte. All rights reserved.
|
||||
//
|
||||
|
||||
#ifndef MemoryMap_hpp
|
||||
#define MemoryMap_hpp
|
||||
|
||||
namespace Amiga {
|
||||
|
||||
struct MemoryMap {
|
||||
public:
|
||||
std::array<uint8_t, 512*1024> chip_ram{};
|
||||
std::array<uint8_t, 512*1024> kickstart{0xff};
|
||||
|
||||
struct MemoryRegion {
|
||||
uint8_t *contents = nullptr;
|
||||
unsigned int read_write_mask = 0;
|
||||
} regions[64]; // i.e. top six bits are used as an index.
|
||||
|
||||
MemoryMap() {
|
||||
// Address spaces that matter:
|
||||
//
|
||||
// 00'0000 – 08'0000: chip RAM. [or overlayed KickStart]
|
||||
// – 10'0000: extended chip ram for ECS.
|
||||
// – 20'0000: auto-config space (/fast RAM).
|
||||
// ...
|
||||
// bf'd000 – c0'0000: 8250s.
|
||||
// c0'0000 – d8'0000: pseudo-fast RAM.
|
||||
// ...
|
||||
// dc'0000 – dd'0000: optional real-time clock.
|
||||
// df'f000 - e0'0000: custom chip registers.
|
||||
// ...
|
||||
// f0'0000 — : 512kb Kickstart (or possibly just an extra 512kb reserved for hypothetical 1mb Kickstart?).
|
||||
// f8'0000 — : 256kb Kickstart if 2.04 or higher.
|
||||
// fc'0000 – : 256kb Kickstart otherwise.
|
||||
set_region(0xfc'0000, 0x1'00'0000, kickstart.data(), CPU::MC68000::Microcycle::PermitRead);
|
||||
reset();
|
||||
}
|
||||
|
||||
void reset() {
|
||||
set_overlay(true);
|
||||
}
|
||||
|
||||
void set_overlay(bool enabled) {
|
||||
if(overlay_ == enabled) {
|
||||
return;
|
||||
}
|
||||
overlay_ = enabled;
|
||||
|
||||
if(enabled) {
|
||||
set_region(0x00'0000, 0x08'0000, kickstart.data(), CPU::MC68000::Microcycle::PermitRead);
|
||||
} else {
|
||||
// Mirror RAM to fill out the address range up to $20'0000.
|
||||
set_region(0x00'0000, 0x08'0000, chip_ram.data(), CPU::MC68000::Microcycle::PermitRead | CPU::MC68000::Microcycle::PermitWrite);
|
||||
set_region(0x08'0000, 0x10'0000, chip_ram.data(), CPU::MC68000::Microcycle::PermitRead | CPU::MC68000::Microcycle::PermitWrite);
|
||||
set_region(0x10'0000, 0x18'0000, chip_ram.data(), CPU::MC68000::Microcycle::PermitRead | CPU::MC68000::Microcycle::PermitWrite);
|
||||
set_region(0x18'0000, 0x20'0000, chip_ram.data(), CPU::MC68000::Microcycle::PermitRead | CPU::MC68000::Microcycle::PermitWrite);
|
||||
}
|
||||
}
|
||||
|
||||
private:
|
||||
bool overlay_ = false;
|
||||
|
||||
void set_region(int start, int end, uint8_t *base, unsigned int read_write_mask) {
|
||||
assert(!(start & ~0xfc'0000));
|
||||
assert(!((end - (1 << 18)) & ~0xfc'0000));
|
||||
|
||||
base -= start;
|
||||
for(int c = start >> 18; c < end >> 18; c++) {
|
||||
regions[c].contents = base;
|
||||
regions[c].read_write_mask = read_write_mask;
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
}
|
||||
#endif /* MemoryMap_hpp */
|
||||
@ -2007,6 +2007,7 @@
|
||||
4BCF1FA31DADC3DD0039D2E7 /* Oric.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = Oric.hpp; sourceTree = "<group>"; };
|
||||
4BD060A51FE49D3C006E14BE /* Speaker.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = Speaker.hpp; sourceTree = "<group>"; };
|
||||
4BD0FBC2233706A200148981 /* CSApplication.m */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.objc; path = CSApplication.m; sourceTree = "<group>"; };
|
||||
4BD1552E270B14AC00410C6E /* MemoryMap.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = MemoryMap.hpp; sourceTree = "<group>"; };
|
||||
4BD191D9219113B80042E144 /* OpenGL.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = OpenGL.hpp; sourceTree = "<group>"; };
|
||||
4BD191F22191180E0042E144 /* ScanTarget.cpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.cpp; path = ScanTarget.cpp; sourceTree = "<group>"; };
|
||||
4BD191F32191180E0042E144 /* ScanTarget.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = ScanTarget.hpp; sourceTree = "<group>"; };
|
||||
@ -4305,6 +4306,7 @@
|
||||
4BC6236A26F178DA00F83DFE /* DMADevice.hpp */,
|
||||
4B9EC0E926B384080060A31F /* Keyboard.hpp */,
|
||||
4BC6237026F94A5B00F83DFE /* Minterms.h */,
|
||||
4BD1552E270B14AC00410C6E /* MemoryMap.hpp */,
|
||||
);
|
||||
path = Amiga;
|
||||
sourceTree = "<group>";
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user