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Implements RMB and SMB, and fixes SBC (zero).

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This commit is contained in:
Thomas Harte 2018-08-10 22:13:51 -04:00
parent 90094529a5
commit 5d6e479338
4 changed files with 21 additions and 2 deletions
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2
OSBindings/Mac/Clock SignalTests/KlausDormannTests.swift
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@ -95,6 +95,8 @@ class KlausDormannTests: XCTestCase {
case 0x1d88: return "TRB set Z flag incorrectly" case 0x1d88: return "TRB set Z flag incorrectly"
case 0x1e7c: return "RMB set flags incorrectly" case 0x1e7c: return "RMB set flags incorrectly"
case 0x2245: return "CMP (zero) didn't work"
case 0: return "Didn't find tests" case 0: return "Didn't find tests"
default: return "Unknown error at \(String(format:"%04x", address))" default: return "Unknown error at \(String(format:"%04x", address))"
} }

9
Processors/6502/Implementation/6502Implementation.hpp
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@ -253,6 +253,15 @@ if(number_of_cycles <= Cycles(0)) break;
operand_ |= a_; operand_ |= a_;
continue; continue;
// MARK: - RMB and SMB
case OperationRMB:
operand_ &= ~(1 << (operation_ >> 4));
continue;
case OperationSMB:
operand_ |= 1 << ((operation_ >> 4)&7);
continue;
// MARK: - ADC/SBC (and INS) // MARK: - ADC/SBC (and INS)
case OperationINS: case OperationINS:

10
Processors/6502/Implementation/6502Storage.cpp
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@ -285,7 +285,7 @@ ProcessorStorage::ProcessorStorage(Personality personality) {
Install(0x92, ZeroIndirectWrite(OperationSTA)); Install(0x92, ZeroIndirectWrite(OperationSTA));
Install(0xb2, ZeroIndirectRead(OperationLDA)); Install(0xb2, ZeroIndirectRead(OperationLDA));
Install(0xd2, ZeroIndirectRead(OperationCMP)); Install(0xd2, ZeroIndirectRead(OperationCMP));
Install(0xd2, ZeroIndirectRead(OperationSBC)); Install(0xf2, ZeroIndirectRead(OperationSBC));
// Add STZ. // Add STZ.
Install(0x9c, AbsoluteWrite(OperationSTZ)); Install(0x9c, AbsoluteWrite(OperationSTZ));
@ -303,6 +303,14 @@ ProcessorStorage::ProcessorStorage(Personality personality) {
Install(0x0c, AbsoluteReadModifyWrite(OperationTSB)); Install(0x0c, AbsoluteReadModifyWrite(OperationTSB));
Install(0x14, ZeroReadModifyWrite(OperationTRB)); Install(0x14, ZeroReadModifyWrite(OperationTRB));
Install(0x1c, AbsoluteReadModifyWrite(OperationTRB)); Install(0x1c, AbsoluteReadModifyWrite(OperationTRB));
// Add RMB and SMB.
for(int c = 0x07; c <= 0x77; c += 0x10) {
Install(c, ZeroReadModifyWrite(OperationRMB));
}
for(int c = 0x87; c <= 0xf7; c += 0x10) {
Install(c, ZeroReadModifyWrite(OperationSMB));
}
} }
#undef Install #undef Install
} }

2
Processors/6502/Implementation/6502Storage.hpp
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@ -53,7 +53,7 @@ class ProcessorStorage {
OperationSAX, OperationSHA, OperationSAX, OperationSHA,
OperationSHX, OperationSHY, OperationSHS, OperationCMP, OperationSHX, OperationSHY, OperationSHS, OperationCMP,
OperationCPX, OperationCPY, OperationBIT, OperationBITNoNV, OperationCPX, OperationCPY, OperationBIT, OperationBITNoNV,
OperationASL, OperationASL, OperationRMB, OperationSMB,
OperationASO, OperationROL, OperationRLA, OperationLSR, OperationASO, OperationROL, OperationRLA, OperationLSR,
OperationLSE, OperationASR, OperationROR, OperationRRA, OperationLSE, OperationASR, OperationROR, OperationRRA,
OperationCLC, OperationCLI, OperationCLV, OperationCLD, OperationCLC, OperationCLI, OperationCLV, OperationCLD,