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https://github.com/TomHarte/CLK.git
synced 2024-11-26 08:49:37 +00:00
Shunted a few more things onto the stack.
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parent
9a82f028aa
commit
5db0f9e2d5
@ -552,6 +552,11 @@ template <class T> class Processor {
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unsigned int scheduleProgramProgramCounter = _scheduleProgramProgramCounter;
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uint8_t operand = _operand;
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uint8_t operation = _operation;
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RegisterPair address = _address;
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RegisterPair nextAddress = _nextAddress;
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BusOperation nextBusOperation = _nextBusOperation;
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uint16_t busAddress = _busAddress;
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uint8_t *busValue = _busValue;
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#define checkSchedule(op) \
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if(!_scheduledPrograms[scheduleProgramsReadPointer]) {\
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@ -575,25 +580,25 @@ template <class T> class Processor {
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while(number_of_cycles > 0) {
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while (_ready_is_active && number_of_cycles > 0) {
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number_of_cycles -= static_cast<T *>(this)->perform_bus_operation(BusOperation::Ready, _busAddress, _busValue);
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number_of_cycles -= static_cast<T *>(this)->perform_bus_operation(BusOperation::Ready, busAddress, busValue);
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}
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while (!_ready_is_active && number_of_cycles > 0) {
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if (_nextBusOperation != BusOperation::None) {
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if (nextBusOperation != BusOperation::None) {
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_irq_request_history[0] = _irq_request_history[1];
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_irq_request_history[1] = _irq_line_is_enabled && !_interruptFlag;
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number_of_cycles -= static_cast<T *>(this)->perform_bus_operation(_nextBusOperation, _busAddress, _busValue);
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_nextBusOperation = BusOperation::None;
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number_of_cycles -= static_cast<T *>(this)->perform_bus_operation(nextBusOperation, busAddress, busValue);
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nextBusOperation = BusOperation::None;
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}
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const MicroOp cycle = program[scheduleProgramProgramCounter];
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scheduleProgramProgramCounter++;
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#define read_op(val, addr) _nextBusOperation = BusOperation::ReadOpcode; _busAddress = addr; _busValue = &val
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#define read_mem(val, addr) _nextBusOperation = BusOperation::Read; _busAddress = addr; _busValue = &val
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#define throwaway_read(addr) _nextBusOperation = BusOperation::Read; _busAddress = addr; _busValue = &throwaway_target
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#define write_mem(val, addr) _nextBusOperation = BusOperation::Write; _busAddress = addr; _busValue = &val
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#define read_op(val, addr) nextBusOperation = BusOperation::ReadOpcode; busAddress = addr; busValue = &val
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#define read_mem(val, addr) nextBusOperation = BusOperation::Read; busAddress = addr; busValue = &val
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#define throwaway_read(addr) nextBusOperation = BusOperation::Read; busAddress = addr; busValue = &throwaway_target
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#define write_mem(val, addr) nextBusOperation = BusOperation::Write; busAddress = addr; busValue = &val
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switch(cycle) {
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@ -664,8 +669,8 @@ template <class T> class Processor {
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case OperationSetFlagsFromA: _zeroResult = _negativeResult = _a; break;
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case CycleIncrementPCAndReadStack: _pc.full++; throwaway_read(_s | 0x100); break;
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case CycleReadPCLFromAddress: read_mem(_pc.bytes.low, _address.full); break;
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case CycleReadPCHFromAddress: _address.bytes.low++; read_mem(_pc.bytes.high, _address.full); break;
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case CycleReadPCLFromAddress: read_mem(_pc.bytes.low, address.full); break;
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case CycleReadPCHFromAddress: address.bytes.low++; read_mem(_pc.bytes.high, address.full); break;
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case CycleReadAndIncrementPC: {
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uint16_t oldPC = _pc.full;
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@ -703,10 +708,10 @@ template <class T> class Processor {
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case OperationSTX: operand = _x; break;
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case OperationSTY: operand = _y; break;
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case OperationSAX: operand = _a & _x; break;
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case OperationSHA: operand = _a & _x & (_address.bytes.high+1); break;
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case OperationSHX: operand = _x & (_address.bytes.high+1); break;
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case OperationSHY: operand = _y & (_address.bytes.high+1); break;
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case OperationSHS: _s = _a & _x; operand = _s & (_address.bytes.high+1); break;
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case OperationSHA: operand = _a & _x & (address.bytes.high+1); break;
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case OperationSHX: operand = _x & (address.bytes.high+1); break;
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case OperationSHY: operand = _y & (address.bytes.high+1); break;
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case OperationSHS: _s = _a & _x; operand = _s & (address.bytes.high+1); break;
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case OperationLXA:
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_a = _x = (_a | 0xee) & operand;
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@ -895,43 +900,43 @@ template <class T> class Processor {
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#pragma mark - Addressing Mode Work
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case CycleAddXToAddressLow:
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_nextAddress.full = _address.full + _x;
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_address.bytes.low = _nextAddress.bytes.low;
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if (_address.bytes.high != _nextAddress.bytes.high) {
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throwaway_read(_address.full);
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nextAddress.full = address.full + _x;
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address.bytes.low = nextAddress.bytes.low;
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if (address.bytes.high != nextAddress.bytes.high) {
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throwaway_read(address.full);
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}
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break;
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case CycleAddXToAddressLowRead:
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_nextAddress.full = _address.full + _x;
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_address.bytes.low = _nextAddress.bytes.low;
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throwaway_read(_address.full);
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nextAddress.full = address.full + _x;
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address.bytes.low = nextAddress.bytes.low;
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throwaway_read(address.full);
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break;
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case CycleAddYToAddressLow:
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_nextAddress.full = _address.full + _y;
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_address.bytes.low = _nextAddress.bytes.low;
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if (_address.bytes.high != _nextAddress.bytes.high) {
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throwaway_read(_address.full);
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nextAddress.full = address.full + _y;
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address.bytes.low = nextAddress.bytes.low;
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if (address.bytes.high != nextAddress.bytes.high) {
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throwaway_read(address.full);
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}
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break;
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case CycleAddYToAddressLowRead:
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_nextAddress.full = _address.full + _y;
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_address.bytes.low = _nextAddress.bytes.low;
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throwaway_read(_address.full);
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nextAddress.full = address.full + _y;
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address.bytes.low = nextAddress.bytes.low;
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throwaway_read(address.full);
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break;
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case OperationCorrectAddressHigh:
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_address.full = _nextAddress.full;
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address.full = nextAddress.full;
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break;
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case CycleIncrementPCFetchAddressLowFromOperand:
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_pc.full++;
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read_mem(_address.bytes.low, operand);
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read_mem(address.bytes.low, operand);
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break;
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case CycleAddXToOperandFetchAddressLow:
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operand += _x;
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read_mem(_address.bytes.low, operand);
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read_mem(address.bytes.low, operand);
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break;
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case CycleIncrementOperandFetchAddressHigh:
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operand++;
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read_mem(_address.bytes.high, operand);
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read_mem(address.bytes.high, operand);
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break;
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case CycleIncrementPCReadPCHLoadPCL: // deliberate fallthrough
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_pc.full++;
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@ -942,37 +947,37 @@ template <class T> class Processor {
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} break;
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case CycleReadAddressHLoadAddressL:
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_address.bytes.low = operand; _pc.full++;
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read_mem(_address.bytes.high, _pc.full);
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address.bytes.low = operand; _pc.full++;
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read_mem(address.bytes.high, _pc.full);
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break;
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case CycleLoadAddressAbsolute: {
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uint16_t nextPC = _pc.full+1;
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_pc.full += 2;
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_address.bytes.low = operand;
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read_mem(_address.bytes.high, nextPC);
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address.bytes.low = operand;
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read_mem(address.bytes.high, nextPC);
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} break;
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case OperationLoadAddressZeroPage:
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_pc.full++;
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_address.full = operand;
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address.full = operand;
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break;
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case CycleLoadAddessZeroX:
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_pc.full++;
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_address.full = (operand + _x)&0xff;
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address.full = (operand + _x)&0xff;
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throwaway_read(operand);
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break;
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case CycleLoadAddessZeroY:
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_pc.full++;
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_address.full = (operand + _y)&0xff;
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address.full = (operand + _y)&0xff;
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throwaway_read(operand);
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break;
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case OperationIncrementPC: _pc.full++; break;
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case CycleFetchOperandFromAddress: read_mem(operand, _address.full); break;
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case CycleWriteOperandToAddress: write_mem(operand, _address.full); break;
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case CycleFetchOperandFromAddress: read_mem(operand, address.full); break;
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case CycleWriteOperandToAddress: write_mem(operand, address.full); break;
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case OperationCopyOperandFromA: operand = _a; break;
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case OperationCopyOperandToA: _a = operand; break;
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@ -990,11 +995,11 @@ template <class T> class Processor {
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case OperationBEQ: BRA(!_zeroResult); break;
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case CycleAddSignedOperandToPC:
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_nextAddress.full = (uint16_t)(_pc.full + (int8_t)operand);
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_pc.bytes.low = _nextAddress.bytes.low;
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if(_nextAddress.bytes.high != _pc.bytes.high) {
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nextAddress.full = (uint16_t)(_pc.full + (int8_t)operand);
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_pc.bytes.low = nextAddress.bytes.low;
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if(nextAddress.bytes.high != _pc.bytes.high) {
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uint16_t halfUpdatedPc = _pc.full;
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_pc.full = _nextAddress.full;
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_pc.full = nextAddress.full;
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throwaway_read(halfUpdatedPc);
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}
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break;
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@ -1041,7 +1046,7 @@ template <class T> class Processor {
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break;
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}
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if (isReadOperation(_nextBusOperation) && _ready_line_is_enabled) {
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if (isReadOperation(nextBusOperation) && _ready_line_is_enabled) {
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_ready_is_active = true;
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}
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}
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@ -1051,6 +1056,11 @@ template <class T> class Processor {
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_scheduleProgramProgramCounter = scheduleProgramProgramCounter;
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_operand = operand;
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_operation = operation;
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_address = address;
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_nextAddress = nextAddress;
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_nextBusOperation = nextBusOperation;
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_busAddress = busAddress;
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_busValue = busValue;
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}
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}
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