From 5f807b6e4732ac1c5ff9d2ab14614b570d5eb21d Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Fri, 8 Jan 2021 23:02:06 -0500 Subject: [PATCH] Ensures that the operand is the only thing failing in decoding of the first instruction. --- OSBindings/Mac/Clock SignalTests/x86DecoderTests.mm | 12 +++++++++++- Processors/Decoders/x86/x86.cpp | 1 + 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/OSBindings/Mac/Clock SignalTests/x86DecoderTests.mm b/OSBindings/Mac/Clock SignalTests/x86DecoderTests.mm index b8f947f95..25688c417 100644 --- a/OSBindings/Mac/Clock SignalTests/x86DecoderTests.mm +++ b/OSBindings/Mac/Clock SignalTests/x86DecoderTests.mm @@ -15,6 +15,8 @@ namespace { using Operation = CPU::Decoder::x86::Operation; using Instruction = CPU::Decoder::x86::Instruction; + using Source = CPU::Decoder::x86::Source; + using Size = CPU::Decoder::x86::Size; } @interface x86DecoderTests : XCTestCase @@ -31,7 +33,13 @@ namespace { // MARK: - Specific instruction asserts. -/* ... TODO ... */ +- (void)assert:(Instruction &)instruction operation:(Operation)operation size:(int)size operand:(uint16_t)operand destination:(Source)destination { + XCTAssertEqual(instruction.operation, operation); + XCTAssertEqual(instruction.operation_size(), CPU::Decoder::x86::Size(size)); + XCTAssertEqual(instruction.destination(), destination); + XCTAssertEqual(instruction.source(), Source::Immediate); + XCTAssertEqual(instruction.operand(), operand); +} // MARK: - Decoder @@ -82,6 +90,8 @@ namespace { // 68 instructions are expected. XCTAssertEqual(instructions.size(), 63); + [self assert:instructions[0] operation:Operation::SUB size:2 operand:0xea77 destination:Source::AX]; + // sub $0xea77,%ax // jb 0x00000001 // dec %bx diff --git a/Processors/Decoders/x86/x86.cpp b/Processors/Decoders/x86/x86.cpp index ae890a476..d4814f388 100644 --- a/Processors/Decoders/x86/x86.cpp +++ b/Processors/Decoders/x86/x86.cpp @@ -37,6 +37,7 @@ std::pair Decoder::decode(const uint8_t *source, size_t length /// Handles instructions of the form rr, kk and rr, jjkk, i.e. a destination register plus an operand. #define RegData(op, dest, size) \ SetOpSrcDestSize(op, DirectAddress, dest, size); \ + source_ = Source::Immediate; \ operand_size_ = size; \ phase_ = Phase::AwaitingDisplacementOrOperand