6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-30 04:50:08 +00:00
Code Issues Projects Releases Wiki Activity

Increases compile-time logging options.

Browse Source
This commit is contained in:
Thomas Harte 2021-08-01 21:22:33 -04:00
parent 57dd38aef2
commit 60b09d9bb0
1 changed files with 36 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
Processors/6502/AllRAM/6502AllRAM.cpp
View File

@ -14,11 +14,15 @@
#include "../../../Components/6526/6526.hpp" #include "../../../Components/6526/6526.hpp"
//#define BE_NOISY //#define BE_NOISY
using namespace CPU::MOS6502; using namespace CPU::MOS6502;
namespace { namespace {
static constexpr bool LogAllReads = false;
static constexpr bool LogAllWrites = false;
static constexpr bool LogCIAAccesses = true;
static constexpr bool LogProgramCounter = false;
using Type = CPU::MOS6502Esque::Type; using Type = CPU::MOS6502Esque::Type;
template <Type type, bool has_cias> class ConcreteAllRAMProcessor: public AllRAMProcessor, public BusHandler { template <Type type, bool has_cias> class ConcreteAllRAMProcessor: public AllRAMProcessor, public BusHandler {
@ -41,14 +45,14 @@ template <Type type, bool has_cias> class ConcreteAllRAMProcessor: public AllRAM
if(isAccessOperation(operation)) { if(isAccessOperation(operation)) {
if(operation == BusOperation::ReadOpcode) { if(operation == BusOperation::ReadOpcode) {
#ifdef BE_NOISY if constexpr (LogProgramCounter) {
printf("[%04x] %02x a:%04x x:%04x y:%04x p:%02x s:%02x\n", address, memory_[address], printf("[%04x] %02x a:%04x x:%04x y:%04x p:%02x s:%02x\n", address, memory_[address],
mos6502_.get_value_of_register(Register::A), mos6502_.get_value_of_register(Register::A),
mos6502_.get_value_of_register(Register::X), mos6502_.get_value_of_register(Register::X),
mos6502_.get_value_of_register(Register::Y), mos6502_.get_value_of_register(Register::Y),
mos6502_.get_value_of_register(Register::Flags) & 0xff, mos6502_.get_value_of_register(Register::Flags) & 0xff,
mos6502_.get_value_of_register(Register::StackPointer) & 0xff); mos6502_.get_value_of_register(Register::StackPointer) & 0xff);
#endif }
check_address_for_trap(address); check_address_for_trap(address);
--instructions_; --instructions_;
} }
@ -59,32 +63,44 @@ template <Type type, bool has_cias> class ConcreteAllRAMProcessor: public AllRAM
if constexpr (has_cias) { if constexpr (has_cias) {
if((address & 0xff00) == 0xdc00) { if((address & 0xff00) == 0xdc00) {
*value = cia1_.read(address); *value = cia1_.read(address);
if constexpr (LogCIAAccesses) {
printf("[%d] CIA1: %04x -> %02x\n", timestamp_.as<int>(), address, *value);
}
} else if((address & 0xff00) == 0xdd00) { } else if((address & 0xff00) == 0xdd00) {
*value = cia2_.read(address); *value = cia2_.read(address);
if constexpr (LogCIAAccesses) {
printf("[%d] CIA2: %04x -> %02x\n", timestamp_.as<int>(), address, *value);
}
}
} }
} if constexpr (LogAllReads) {
#ifdef BE_NOISY
// if((address&0xff00) == 0x100) { // if((address&0xff00) == 0x100) {
printf("%04x -> %02x\n", address, *value); printf("%04x -> %02x\n", address, *value);
// } // }
#endif }
} else { } else {
memory_[address] = *value; memory_[address] = *value;
if constexpr (has_cias) { if constexpr (has_cias) {
if((address & 0xff00) == 0xdc00) { if((address & 0xff00) == 0xdc00) {
cia1_.write(address, *value); cia1_.write(address, *value);
if constexpr (LogCIAAccesses) {
printf("[%d] CIA1: %04x <- %02x\n", timestamp_.as<int>(), address, *value);
}
} else if((address & 0xff00) == 0xdd00) { } else if((address & 0xff00) == 0xdd00) {
cia2_.write(address, *value); cia2_.write(address, *value);
if constexpr (LogCIAAccesses) {
printf("[%d] CIA2: %04x <- %02x\n", timestamp_.as<int>(), address, *value);
} }
} }
#ifdef BE_NOISY }
if constexpr (LogAllWrites) {
// if((address&0xff00) == 0x100) { // if((address&0xff00) == 0x100) {
printf("%04x <- %02x\n", address, *value); printf("%04x <- %02x\n", address, *value);
// } // }
#endif }
} }
} }