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Implement registers side.
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@ -37,6 +37,10 @@ enum class Mode {
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/// Combines the ARM registers and status flags into a single whole, given that the architecture
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/// doesn't have the same degree of separation as others.
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///
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/// The PC contained here is always taken to be **the address of the current instruction**,
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/// i.e. disregarding pipeline differences. Appropriate prefetch offsets are left to other code to handle.
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/// This is to try to keep this structure independent of a specific ARM implementation.
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struct Registers {
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public:
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/// Sets the N and Z flags according to the value of @c result.
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@ -74,13 +78,28 @@ struct Registers {
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interrupt_flags_;
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}
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void set_status(uint32_t) {
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/// Sets status bits only, subject to mode.
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void set_status(uint32_t status) {
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// ... in user mode the other flags (I, F, M1, M0) are protected from direct change
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// but in non-user modes these will also be affected, accepting copies of bits 27, 26,
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// 1 and 0 of the result respectively.
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negative_flag_ = status;
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overflow_flag_ = status << 3;
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carry_flag_ = status & ConditionCode::Carry;
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zero_result_ = ~status & ConditionCode::Zero;
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if(mode_ != Mode::User) {
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mode_ = Mode(status & 3);
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interrupt_flags_ = status & (ConditionCode::IRQDisable | ConditionCode::FIQDisable);
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}
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}
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void set_pc(uint32_t) {}
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/// Sets a new PC.
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/// TODO: communicate this onward.
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void set_pc(uint32_t value) {
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active[15] = value & ConditionCode::Address;
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}
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uint32_t pc(uint32_t offset) const {
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return (active[15] + offset) & ConditionCode::Address;
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