From 63ad2e826396da7c8711e11d2fe4629d8a9c098a Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Sun, 30 Oct 2022 11:20:43 -0400
Subject: [PATCH] Decode EXTB.l.

---
 InstructionSets/M68k/Decoder.cpp              | 20 +++++++++++++++++--
 InstructionSets/M68k/Instruction.cpp          |  1 +
 .../68000 Decoding/68020ops.json              | 16 +++++++--------
 3 files changed, 27 insertions(+), 10 deletions(-)

diff --git a/InstructionSets/M68k/Decoder.cpp b/InstructionSets/M68k/Decoder.cpp
index a84c01632..c96ee60ae 100644
--- a/InstructionSets/M68k/Decoder.cpp
+++ b/InstructionSets/M68k/Decoder.cpp
@@ -601,6 +601,11 @@ template <typename Predecoder<model>::OpT op> uint32_t Predecoder<model>::invali
 				AllModesNoAn,
 				Dn
 			>::value;
+
+		case OpT(Operation::EXTbtol):
+			return ~OneOperandMask<
+				Dn
+			>::value;
 	}
 
 	return InvalidOperands;
@@ -1234,6 +1239,14 @@ template <typename Predecoder<model>::OpT op, bool validate> Preinstruction Pred
 				combined_mode(ea_mode, ea_register), ea_register,
 				AddressingMode::DataRegisterDirect, data_register);
 
+		//
+		// MARK: EXTbtol
+		//
+		// b0–b2:		a data register.
+		//
+		case OpT(Operation::EXTbtol):
+			return validated<op, validate>(AddressingMode::DataRegisterDirect, ea_register);
+
 		//
 		// MARK: DIVl
 		//
@@ -1415,12 +1428,15 @@ Preinstruction Predecoder<model>::decode4(uint16_t instruction) {
 	switch(instruction & 0xff8) {
 		case 0x840:	Decode(Op::SWAP);			// 4-185 (p289)
 		case 0x848: DecodeReq(model >= Model::M68010, Op::BKPT);	// 4-54 (p158)
-		case 0x880:	Decode(Op::EXTbtow);		// 4-106 (p210)
-		case 0x8c0:	Decode(Op::EXTwtol);		// 4-106 (p210)
 		case 0xe58:	Decode(Op::UNLINK);			// 4-194 (p298)
 		case 0xe60:	Decode(Op::MOVEtoUSP);		// 6-21 (p475)
 		case 0xe68:	Decode(Op::MOVEfromUSP);	// 6-21 (p475)
 
+		// 4-106 (p210)
+		case 0x880:	Decode(Op::EXTbtow);
+		case 0x8c0:	Decode(Op::EXTwtol);
+		case 0x9c0:	DecodeReq(model >= Model::M68020, Op::EXTbtol);
+
 		// 4-111 (p215)
 		case 0x808:	DecodeReq(model >= Model::M68020, Op::LINKl);
 		case 0xe50:	Decode(Op::LINKw);
diff --git a/InstructionSets/M68k/Instruction.cpp b/InstructionSets/M68k/Instruction.cpp
index e1d195742..b30e0efd5 100644
--- a/InstructionSets/M68k/Instruction.cpp
+++ b/InstructionSets/M68k/Instruction.cpp
@@ -261,6 +261,7 @@ const char *_to_string(Operation operation, bool is_quick) {
 
 		case Operation::EXTbtow:		return "EXT.w";
 		case Operation::EXTwtol:		return "EXT.l";
+		case Operation::EXTbtol:		return "EXTB.l";
 
 		case Operation::LINKw:			return "LINK";
 		case Operation::LINKl:			return "LINK.l";
diff --git a/OSBindings/Mac/Clock SignalTests/68000 Decoding/68020ops.json b/OSBindings/Mac/Clock SignalTests/68000 Decoding/68020ops.json
index 123b1d9af..b0b77f5d4 100644
--- a/OSBindings/Mac/Clock SignalTests/68000 Decoding/68020ops.json	
+++ b/OSBindings/Mac/Clock SignalTests/68000 Decoding/68020ops.json	
@@ -18879,14 +18879,14 @@
 	"49bd": "None",
 	"49be": "None",
 	"49bf": "None",
-	"49c0": "None",
-	"49c1": "None",
-	"49c2": "None",
-	"49c3": "None",
-	"49c4": "None",
-	"49c5": "None",
-	"49c6": "None",
-	"49c7": "None",
+	"49c0": "EXTB.l D0",
+	"49c1": "EXTB.l D1",
+	"49c2": "EXTB.l D2",
+	"49c3": "EXTB.l D3",
+	"49c4": "EXTB.l D4",
+	"49c5": "EXTB.l D5",
+	"49c6": "EXTB.l D6",
+	"49c7": "EXTB.l D7",
 	"49c8": "None",
 	"49c9": "None",
 	"49ca": "None",