diff --git a/Machines/AmstradCPC/AmstradCPC.cpp b/Machines/AmstradCPC/AmstradCPC.cpp
index 87c05bc7e..e8f78f5d4 100644
--- a/Machines/AmstradCPC/AmstradCPC.cpp
+++ b/Machines/AmstradCPC/AmstradCPC.cpp
@@ -305,7 +305,7 @@ class CRTCBusHandler {
 			// Per Interrupts in the CPC: "to be confirmed: does gate array count positive or negative edge transitions of HSYNC signal?";
 			// if you take it as given that display mode is latched as a result of hsync then Pipe Mania seems to imply that the count
 			// occurs on a leading edge and the mode lock on a trailing.
-			if(was_hsync_ && !state.hsync) {
+			if(!was_hsync_ && state.hsync) {
 				interrupt_timer_.signal_hsync();
 			}