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Take improved guess at address error stacking order.

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This commit is contained in:
Thomas Harte 2022-06-09 16:17:09 -04:00
parent a59ad06438
commit 64053d697f
2 changed files with 16 additions and 8 deletions
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3
OSBindings/Mac/Clock SignalTests/68000Tests.mm
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@ -189,6 +189,9 @@
// PC.
XCTAssertEqual(stack_frame[5], 0x0000);
XCTAssertEqual(stack_frame[6], 0x1004);
// Check that A7 ended up in the proper location.
XCTAssertEqual(_machine->get_processor_state().registers.stack_pointer(), 0x1f8);
}
- (void)testShiftDuration {

21
Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
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@ -461,8 +461,13 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
// 2) captured state;
// 3) program counter high;
// 4) instruction register;
// 5) function code;
// 6) access address?
// 5) access address low;
// 6) function code;
// 7) access address high?
//
// Noteworthy in this guess: access code and function code are written in
// the same interleaved order as program counter and captured status register,
// which is the order that I know to be correct for a standard exception.
IdleBus(2);
@ -506,15 +511,15 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
((bus_error_.operation & Microcycle::IsProgram) ? 0x08 : 0x00) |
((bus_error_.operation & Microcycle::IsProgram) ? 0x02 : 0x01) |
((captured_status_.w & InstructionSet::M68k::ConditionCode::Supervisor) ? 0x04 : 0x00);
registers_[15].l -= 6;
Access(temporary_value_.low); // ns [function code]
temporary_address_.l = *bus_error_.address;
registers_[15].l += 4;
Access(temporary_address_.low); // ns [error address.l]
registers_[15].l -= 2;
Access(temporary_address_.low); // ns [error address.l]
registers_[15].l -= 4;
Access(temporary_value_.low); // ns [function code]
registers_[15].l += 2;
Access(temporary_address_.high); // nS [error address.h]
registers_[15].l -= 2;