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mirror of https://github.com/TomHarte/CLK.git synced 2024-06-16 15:29:34 +00:00

Adjust means of waiting out address.

This commit is contained in:
Thomas Harte 2024-03-17 22:14:07 -04:00
parent 7b1f800387
commit 64e025484a

View File

@ -78,7 +78,7 @@ void Bus::set_clock_data(bool clock_pulled, bool data_pulled) {
active_peripheral_ = pair->second;
peripheral_response_ = 0;
peripheral_bits_ = 2;
peripheral_bits_ = 1;
phase_ = Phase::AwaitingByte;
printf("Waiting for byte\n");
} else {
@ -89,11 +89,11 @@ void Bus::set_clock_data(bool clock_pulled, bool data_pulled) {
break;
case Phase::AwaitingByte:
if(data_ && clock_) {
// Run down the clock on the acknowledge bit.
if(!peripheral_bits_) {
printf("Beginning byte\n");
phase_ = Phase::CollectingByte;
input_count_ = 0;
input_ = 0;
}
break;