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https://github.com/TomHarte/CLK.git
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Adjust means of waiting out address.
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parent
7b1f800387
commit
64e025484a
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@ -78,7 +78,7 @@ void Bus::set_clock_data(bool clock_pulled, bool data_pulled) {
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active_peripheral_ = pair->second;
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active_peripheral_ = pair->second;
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peripheral_response_ = 0;
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peripheral_response_ = 0;
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peripheral_bits_ = 2;
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peripheral_bits_ = 1;
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phase_ = Phase::AwaitingByte;
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phase_ = Phase::AwaitingByte;
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printf("Waiting for byte\n");
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printf("Waiting for byte\n");
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} else {
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} else {
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@ -89,11 +89,11 @@ void Bus::set_clock_data(bool clock_pulled, bool data_pulled) {
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break;
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break;
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case Phase::AwaitingByte:
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case Phase::AwaitingByte:
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if(data_ && clock_) {
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// Run down the clock on the acknowledge bit.
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if(!peripheral_bits_) {
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printf("Beginning byte\n");
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printf("Beginning byte\n");
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phase_ = Phase::CollectingByte;
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phase_ = Phase::CollectingByte;
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input_count_ = 0;
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input_count_ = 0;
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input_ = 0;
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}
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}
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break;
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break;
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