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Complete instruction set; consolidate mapper.

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This commit is contained in:
Thomas Harte 2024-02-21 15:32:27 -05:00
parent e986ae2878
commit 6577f68efc
4 changed files with 104 additions and 106 deletions
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17
InstructionSets/ARM/Model.hpp
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@ -1,17 +0,0 @@
//
// Model.hpp
// Clock Signal
//
// Created by Thomas Harte on 16/02/2024.
// Copyright © 2024 Thomas Harte. All rights reserved.
//
#pragma once
namespace InstructionSet::ARM {
enum class Model {
ARM2,
};
}

68
InstructionSets/ARM/Operation.hpp
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@ -1,68 +0,0 @@
//
// Operation.hpp
// Clock Signal
//
// Created by Thomas Harte on 16/02/2024.
// Copyright © 2024 Thomas Harte. All rights reserved.
//
#pragma once
namespace InstructionSet::ARM {
enum class Operation {
/// Rd = Op1 AND Op2.
AND,
/// Rd = Op1 EOR Op2.
EOR,
/// Rd = Op1 - Op2.
SUB,
/// Rd = Op2 - Op1.
RSB,
/// Rd = Op1 + Op2.
ADD,
/// Rd = Op1 + Ord2 + C.
ADC,
/// Rd = Op1 - Op2 + C.
SBC,
/// Rd = Op2 - Op1 + C.
RSC,
/// Set condition codes on Op1 AND Op2.
TST,
/// Set condition codes on Op1 EOR Op2.
TEQ,
/// Set condition codes on Op1 - Op2.
CMP,
/// Set condition codes on Op1 + Op2.
CMN,
/// Rd = Op1 OR Op2.
ORR,
/// Rd = Op2
MOV,
/// Rd = Op1 AND NOT Op2.
BIC,
/// Rd = NOT Op2.
MVN,
MUL, MLA,
B, BL,
LDR, STR,
LDM, STM,
SWI,
CDP,
MRC, MCR,
CoprocessorDataTransfer,
Undefined,
};
enum class Condition {
EQ, NE, CS, CC,
MI, PL, VS, VC,
HI, LS, GE, LT,
GT, LE, AL, NV,
};
}

117
InstructionSets/ARM/Decoder.hpp → InstructionSets/ARM/OperationMapper.hpp
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@ -1,5 +1,5 @@
//
// Decoder.hpp
// OperationMapper.hpp
// Clock Signal
//
// Created by Thomas Harte on 16/02/2024.
@ -8,15 +8,69 @@
#pragma once
#include "Model.hpp"
#include "Operation.hpp"
#include "../../Reflection/Dispatcher.hpp"
#include <array>
namespace InstructionSet::ARM {
enum class Model {
ARM2,
};
enum class Operation {
/// Rd = Op1 AND Op2.
AND,
/// Rd = Op1 EOR Op2.
EOR,
/// Rd = Op1 - Op2.
SUB,
/// Rd = Op2 - Op1.
RSB,
/// Rd = Op1 + Op2.
ADD,
/// Rd = Op1 + Ord2 + C.
ADC,
/// Rd = Op1 - Op2 + C.
SBC,
/// Rd = Op2 - Op1 + C.
RSC,
/// Set condition codes on Op1 AND Op2.
TST,
/// Set condition codes on Op1 EOR Op2.
TEQ,
/// Set condition codes on Op1 - Op2.
CMP,
/// Set condition codes on Op1 + Op2.
CMN,
/// Rd = Op1 OR Op2.
ORR,
/// Rd = Op2
MOV,
/// Rd = Op1 AND NOT Op2.
BIC,
/// Rd = NOT Op2.
MVN,
MUL, MLA,
B, BL,
LDR, STR,
LDM, STM,
SWI,
CDP,
MRC, MCR,
LDC, STC,
Undefined,
};
enum class Condition {
EQ, NE, CS, CC,
MI, PL, VS, VC,
HI, LS, GE, LT,
GT, LE, AL, NV,
};
enum class ShiftType {
LogicalLeft = 0b00,
LogicalRight = 0b01,
@ -204,10 +258,41 @@ struct CoprocessorOperationOrRegisterTransfer {
int coprocessor() { return (opcode_ >> 8) & 0xf; }
int information() { return (opcode_ >> 5) & 0x7; }
protected:
private:
uint32_t opcode_;
};
//
// Coprocessor data transfer.
//
struct CoprocessorDataTransferFlags {
constexpr CoprocessorDataTransferFlags(uint8_t flags) noexcept : flags_(flags) {}
constexpr bool pre_index() { return flag_bit<24>(flags_); }
constexpr bool add_offset() { return flag_bit<23>(flags_); }
constexpr bool transfer_length() { return flag_bit<22>(flags_); }
constexpr bool write_back_address() { return flag_bit<21>(flags_); }
private:
uint8_t flags_;
};
struct CoprocessorDataTransfer {
constexpr CoprocessorDataTransfer(uint32_t opcode) noexcept : opcode_(opcode) {}
int base() { return (opcode_ >> 16) & 0xf; }
int source() { return (opcode_ >> 12) & 0xf; }
int destination() { return (opcode_ >> 12) & 0xf; }
int coprocessor() { return (opcode_ >> 8) & 0xf; }
int offset() { return opcode_ & 0xff; }
private:
uint32_t opcode_;
};
/// Operation mapper; use the free function @c dispatch as defined below.
struct OperationMapper {
template <int i, typename SchedulerT> void dispatch(uint32_t instruction, SchedulerT &scheduler) {
constexpr auto partial = uint32_t(i << 20);
@ -304,6 +389,16 @@ struct OperationMapper {
);
}
}
// Coprocessor data transfers; cf. p.39.
if constexpr (((partial >> 25) & 0b111) == 0b110) {
constexpr bool is_ldc = partial & (1 << 20);
constexpr auto flags = CoprocessorDataTransferFlags(i);
scheduler.template coprocessor_data_transfer<is_ldc ? Operation::LDC : Operation::STC, flags>(
condition,
CoprocessorDataTransfer(instruction)
);
}
}
};
@ -313,12 +408,4 @@ template <typename SchedulerT> void dispatch(uint32_t instruction, SchedulerT &s
Reflection::dispatch(mapper, (instruction >> FlagsStartBit) & 0xff, instruction, scheduler);
}
/*
if(((opcode >> 25) & 0b111) == 0b110) {
result[c] = Operation::CoprocessorDataTransfer;
continue;
}
*/
}

8
OSBindings/Mac/Clock Signal.xcodeproj/project.pbxproj
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@ -1333,10 +1333,8 @@
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4B1EC715255398B000A1F44B /* Sound.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = Sound.hpp; sourceTree = "<group>"; };
4B1EDB431E39A0AC009D6819 /* chip.png */ = {isa = PBXFileReference; lastKnownFileType = image.png; path = chip.png; sourceTree = "<group>"; };
4B2005402B804AA300420C5C /* Decoder.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = Decoder.hpp; sourceTree = "<group>"; };
4B2005402B804AA300420C5C /* OperationMapper.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = OperationMapper.hpp; sourceTree = "<group>"; };
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4B2005452B804DF600420C5C /* Operation.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = Operation.hpp; sourceTree = "<group>"; };
4B2130E0273A7A0A008A77B4 /* Audio.cpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.cpp; path = Audio.cpp; sourceTree = "<group>"; };
4B2130E1273A7A0A008A77B4 /* Audio.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = Audio.hpp; sourceTree = "<group>"; };
4B228CD424D773B30077EF25 /* CSScanTarget.mm */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.objcpp; path = CSScanTarget.mm; sourceTree = "<group>"; };
@ -2760,9 +2758,7 @@
4B20053D2B804A4F00420C5C /* ARM */ = {
isa = PBXGroup;
children = (
4B2005402B804AA300420C5C /* Decoder.hpp */,
4B2005442B804DC900420C5C /* Model.hpp */,
4B2005452B804DF600420C5C /* Operation.hpp */,
4B2005402B804AA300420C5C /* OperationMapper.hpp */,
);
path = ARM;
sourceTree = "<group>";