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mirror of https://github.com/TomHarte/CLK.git synced 2025-02-16 18:30:32 +00:00

Always consume a second cycle in 16-bit mode.

This commit is contained in:
Thomas Harte 2022-06-23 12:46:51 -04:00
parent 2c12a7d968
commit 66775b2c4e

View File

@ -300,8 +300,12 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
data_address_ = instruction_buffer_.value + registers_.x.full + registers_.data_bank;
incorrect_data_address_ = ((data_address_ & 0x00ff) | (instruction_buffer_.value & 0xff00)) + registers_.data_bank;
// If the incorrect address isn't actually incorrect, skip its usage.
if(operation == OperationConstructAbsoluteXRead && data_address_ == incorrect_data_address_) {
// "Add 1 cycle for indexing across page boundaries, or write, or X=0"
// (i.e. don't add 1 cycle if x = 1 and this is a read, and a page boundary wasn't crossed)
if(
operation == OperationConstructAbsoluteXRead &&
data_address_ == incorrect_data_address_ &&
registers_.mx_flags[1]) {
++next_op_;
}
data_address_increment_mask_ = 0xff'ff'ff;
@ -312,8 +316,12 @@ template <typename BusHandler, bool uses_ready_line> void Processor<BusHandler,
data_address_ = instruction_buffer_.value + registers_.y.full + registers_.data_bank;
incorrect_data_address_ = (data_address_ & 0xff) + (instruction_buffer_.value & 0xff00) + registers_.data_bank;
// If the incorrect address isn't actually incorrect, skip its usage.
if(operation == OperationConstructAbsoluteYRead && data_address_ == incorrect_data_address_) {
// "Add 1 cycle for indexing across page boundaries, or write, or X=0"
// (i.e. don't add 1 cycle if x = 1 and this is a read, and a page boundary wasn't crossed)
if(
operation == OperationConstructAbsoluteYRead &&
data_address_ == incorrect_data_address_ &&
registers_.mx_flags[1]) {
++next_op_;
}
data_address_increment_mask_ = 0xff'ff'ff;