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https://github.com/TomHarte/CLK.git
synced 2024-10-06 15:00:05 +00:00
Starts to add a disk controller.
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@ -33,20 +33,16 @@ template <DMAFlag... Flags> struct DMAMask: Mask<DMAFlag, Flags...> {};
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}
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}
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Chipset::Chipset(MemoryMap &map, int input_clock_rate) :
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Chipset::Chipset(MemoryMap &map, int input_clock_rate) :
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cia_a_handler_(map),
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cia_a(cia_a_handler_),
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cia_b(cia_b_handler_),
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blitter_(*this, reinterpret_cast<uint16_t *>(map.chip_ram.data()), map.chip_ram.size() >> 1),
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blitter_(*this, reinterpret_cast<uint16_t *>(map.chip_ram.data()), map.chip_ram.size() >> 1),
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bitplanes_(*this, reinterpret_cast<uint16_t *>(map.chip_ram.data()), map.chip_ram.size() >> 1),
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bitplanes_(*this, reinterpret_cast<uint16_t *>(map.chip_ram.data()), map.chip_ram.size() >> 1),
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copper_(*this, reinterpret_cast<uint16_t *>(map.chip_ram.data()), map.chip_ram.size() >> 1),
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copper_(*this, reinterpret_cast<uint16_t *>(map.chip_ram.data()), map.chip_ram.size() >> 1),
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drives_{
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disk_controller_(Cycles(input_clock_rate)),
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{input_clock_rate, 300, 2, Storage::Disk::Drive::ReadyType::ShugartRDY},
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{input_clock_rate, 300, 2, Storage::Disk::Drive::ReadyType::ShugartRDY},
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{input_clock_rate, 300, 2, Storage::Disk::Drive::ReadyType::ShugartRDY},
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{input_clock_rate, 300, 2, Storage::Disk::Drive::ReadyType::ShugartRDY}
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},
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disk_(*this, reinterpret_cast<uint16_t *>(map.chip_ram.data()), map.chip_ram.size() >> 1),
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disk_(*this, reinterpret_cast<uint16_t *>(map.chip_ram.data()), map.chip_ram.size() >> 1),
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crt_(908, 4, Outputs::Display::Type::PAL50, Outputs::Display::InputDataType::Red4Green4Blue4) {
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crt_(908, 4, Outputs::Display::Type::PAL50, Outputs::Display::InputDataType::Red4Green4Blue4),
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cia_a_handler_(map, disk_controller_),
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cia_b_handler_(disk_controller_),
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cia_a(cia_a_handler_),
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cia_b(cia_b_handler_) {
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}
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}
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Chipset::Changes Chipset::run_for(HalfCycles length) {
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Chipset::Changes Chipset::run_for(HalfCycles length) {
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@ -920,9 +916,9 @@ Outputs::Display::DisplayType Chipset::get_display_type() const {
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return crt_.get_display_type();
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return crt_.get_display_type();
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}
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}
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// MARK: - CIA Handlers.
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// MARK: - CIA A.
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Chipset::CIAAHandler::CIAAHandler(MemoryMap &map) : map_(map) {}
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Chipset::CIAAHandler::CIAAHandler(MemoryMap &map, DiskController &controller) : map_(map), controller_(controller) {}
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void Chipset::CIAAHandler::set_port_output(MOS::MOS6526::Port port, uint8_t value) {
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void Chipset::CIAAHandler::set_port_output(MOS::MOS6526::Port port, uint8_t value) {
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if(port) {
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if(port) {
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@ -965,6 +961,10 @@ void Chipset::CIAAHandler::set_activity_observer(Activity::Observer *observer) {
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}
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}
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}
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}
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// MARK: - CIA B.
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Chipset::CIABHandler::CIABHandler(DiskController &controller) : controller_(controller) {}
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void Chipset::CIABHandler::set_port_output(MOS::MOS6526::Port port, uint8_t value) {
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void Chipset::CIABHandler::set_port_output(MOS::MOS6526::Port port, uint8_t value) {
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if(port) {
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if(port) {
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// Serial port control.
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// Serial port control.
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@ -991,10 +991,42 @@ void Chipset::CIABHandler::set_port_output(MOS::MOS6526::Port port, uint8_t valu
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// b1: DIR
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// b1: DIR
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// b0: /STEP
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// b0: /STEP
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LOG("TODO: Stepping, etc; " << PADHEX(2) << +value);
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LOG("TODO: Stepping, etc; " << PADHEX(2) << +value);
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controller_.set_drive((value >> 3) & 0xf);
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// "[The MTR] signal is nonstandard on the Amiga system.
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// Each drive will latch the motor signal at the time its
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// select signal turns on." — The Hardware Reference Manual.
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previous_select_ = value;
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}
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}
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}
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}
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uint8_t Chipset::CIABHandler::get_port_input(MOS::MOS6526::Port) {
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uint8_t Chipset::CIABHandler::get_port_input(MOS::MOS6526::Port port) {
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LOG("Unexpected input for CIA B ");
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LOG("Unexpected input for CIA B ");
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if(port) {
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return 0xff;
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return 0xff;
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} else {
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return previous_select_;
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}
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}
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// MARK: - Disk Controller.
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Chipset::DiskController::DiskController(Cycles clock_rate) :
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Storage::Disk::Controller(clock_rate) {
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// Add four drives.
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for(int c = 0; c < 4; c++) {
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emplace_drive(clock_rate.as<int>(), 300, 2, Storage::Disk::Drive::ReadyType::ShugartRDY);
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}
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}
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void Chipset::DiskController::process_input_bit(int value) {
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// TODO:
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(void)value;
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}
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void Chipset::DiskController::process_index_hole() {
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// TODO: does the Amiga care?
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}
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}
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@ -16,6 +16,7 @@
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#include "../../Components/6526/6526.hpp"
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#include "../../Components/6526/6526.hpp"
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#include "../../Outputs/CRT/CRT.hpp"
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#include "../../Outputs/CRT/CRT.hpp"
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#include "../../Processors/68000/68000.hpp"
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#include "../../Processors/68000/68000.hpp"
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#include "../../Storage/Disk/Controller/DiskController.hpp"
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#include "../../Storage/Disk/Drive.hpp"
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#include "../../Storage/Disk/Drive.hpp"
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#include "Blitter.hpp"
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#include "Blitter.hpp"
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@ -100,31 +101,6 @@ class Chipset {
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cia_a_handler_.set_activity_observer(observer);
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cia_a_handler_.set_activity_observer(observer);
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}
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}
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private:
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class CIAAHandler: public MOS::MOS6526::PortHandler {
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public:
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CIAAHandler(MemoryMap &map);
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void set_port_output(MOS::MOS6526::Port port, uint8_t value);
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uint8_t get_port_input(MOS::MOS6526::Port port);
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void set_activity_observer(Activity::Observer *observer);
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private:
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MemoryMap &map_;
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Activity::Observer *observer_ = nullptr;
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inline static const std::string led_name = "Power";
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} cia_a_handler_;
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struct CIABHandler: public MOS::MOS6526::PortHandler {
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void set_port_output(MOS::MOS6526::Port port, uint8_t value);
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uint8_t get_port_input(MOS::MOS6526::Port);
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} cia_b_handler_;
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public:
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// CIAs are provided for direct access; it's up to the caller properly
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// to distinguish relevant accesses.
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MOS::MOS6526::MOS6526<CIAAHandler, MOS::MOS6526::Personality::P8250> cia_a;
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MOS::MOS6526::MOS6526<CIABHandler, MOS::MOS6526::Personality::P8250> cia_b;
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private:
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private:
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friend class DMADeviceBase;
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friend class DMADeviceBase;
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@ -242,7 +218,19 @@ class Chipset {
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// MARK: - Disk drives.
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// MARK: - Disk drives.
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Storage::Disk::Drive drives_[4];
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class DiskController: private Storage::Disk::Controller {
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public:
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DiskController(Cycles clock_rate);
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void set_drive(int index_mask) {
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Storage::Disk::Controller::set_drive(index_mask);
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}
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private:
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void process_input_bit(int value) final;
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void process_index_hole() final;
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} disk_controller_;
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class DiskDMA: public DMADevice<1> {
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class DiskDMA: public DMADevice<1> {
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public:
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public:
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@ -271,6 +259,39 @@ class Chipset {
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Outputs::CRT::CRT crt_;
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Outputs::CRT::CRT crt_;
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uint16_t palette_[32]{};
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uint16_t palette_[32]{};
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uint16_t swizzled_palette_[32]{};
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uint16_t swizzled_palette_[32]{};
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// MARK: - CIAs
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private:
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class CIAAHandler: public MOS::MOS6526::PortHandler {
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public:
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CIAAHandler(MemoryMap &map, DiskController &controller);
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void set_port_output(MOS::MOS6526::Port port, uint8_t value);
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uint8_t get_port_input(MOS::MOS6526::Port port);
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void set_activity_observer(Activity::Observer *observer);
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private:
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MemoryMap &map_;
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DiskController &controller_;
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Activity::Observer *observer_ = nullptr;
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inline static const std::string led_name = "Power";
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} cia_a_handler_;
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class CIABHandler: public MOS::MOS6526::PortHandler {
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public:
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CIABHandler(DiskController &controller);
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void set_port_output(MOS::MOS6526::Port port, uint8_t value);
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uint8_t get_port_input(MOS::MOS6526::Port);
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private:
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DiskController &controller_;
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uint8_t previous_select_ = 0;
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} cia_b_handler_;
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public:
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// CIAs are provided for direct access; it's up to the caller properly
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// to distinguish relevant accesses.
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MOS::MOS6526::MOS6526<CIAAHandler, MOS::MOS6526::Personality::P8250> cia_a;
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MOS::MOS6526::MOS6526<CIABHandler, MOS::MOS6526::Personality::P8250> cia_b;
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};
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};
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}
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}
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