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mirror of https://github.com/TomHarte/CLK.git synced 2026-04-21 17:16:44 +00:00

Filled in most of the loads.

This commit is contained in:
Thomas Harte
2017-05-19 22:57:43 -04:00
parent bc3b5f3e35
commit 6766845e21
2 changed files with 106 additions and 37 deletions
+2 -1
View File
@@ -16,9 +16,10 @@ AllRAMProcessor::AllRAMProcessor() : ::CPU::AllRAMProcessor(65536) {}
int AllRAMProcessor::perform_machine_cycle(const MachineCycle *cycle) {
switch(cycle->operation) {
case BusOperation::ReadOpcode:
printf("! ");
check_address_for_trap(*cycle->address);
case BusOperation::Read:
printf("r %04x\n", *cycle->address);
printf("r %04x [%02x]\n", *cycle->address, memory_[*cycle->address]);
*cycle->value = memory_[*cycle->address];
break;
case BusOperation::Write: