Sketches out the absolute basics of an SCC interface.

Components/8530/z8530.cpp

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+//
+//  8530.cpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 07/06/2019.
+//  Copyright © 2019 Thomas Harte. All rights reserved.
+//
+
+#include "z8530.hpp"
+
+using namespace Zilog::SCC;
+
+void z8530::reset() {
+}
+
+std::uint8_t z8530::read(int address) {
+	return channels_[address & 1].read(address & 2);
+}
+
+void z8530::write(int address, std::uint8_t value) {
+	channels_[address & 1].write(address & 2, pointer_, value);
+
+	/*
+		Control register 0, which includes the pointer bits,
+		is decoded here because there's only one set of pointer bits.
+	*/
+	if(!(address & 2)) {
+		if(pointer_) {
+			pointer_ = 0;
+		} else {
+			pointer_ = value & 7;
+		}
+	}
+}
+
+uint8_t z8530::Channel::read(bool data) {
+	// If this is a data read, just return it.
+	if(data) return data_;
+
+	// Otherwise, this is a control read...
+	return 0x00;
+}
+
+void z8530::Channel::write(bool data, uint8_t pointer, uint8_t value) {
+	if(data) {
+		data_ = value;
+		return;
+	}
+}

Components/8530/z8530.hpp

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+//
+//  z8530.hpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 07/06/2019.
+//  Copyright © 2019 Thomas Harte. All rights reserved.
+//
+
+#ifndef z8530_hpp
+#define z8530_hpp
+
+#include <cstdint>
+
+namespace Zilog {
+namespace SCC {
+
+/*!
+	Models the Zilog 8530 SCC, a serial adaptor.
+*/
+class z8530 {
+	public:
+		void reset();
+
+		/*
+			Notes on addressing below:
+
+			There's no inherent ordering of the two 'address' lines,
+			A/B and C/D, but the methods below assume:
+
+				A/B = A0
+				C/D = A1
+		*/
+
+		std::uint8_t read(int address);
+		void write(int address, std::uint8_t value);
+
+	private:
+		class Channel {
+			public:
+				uint8_t read(bool data);
+				void write(bool data, uint8_t pointer, uint8_t value);
+
+			private:
+				uint8_t data_ = 0xff;
+		} channels_[2];
+		uint8_t pointer_ = 0;
+};
+
+}
+}
+
+
+#endif /* z8530_hpp */