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https://github.com/TomHarte/CLK.git
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Makes an attempt to perform MSX memory paging.
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@ -20,13 +20,6 @@
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namespace MSX {
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class i8255PortHandler: public Intel::i8255::PortHandler {
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public:
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void set_value(int port, uint8_t value) {
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printf("8255 set %d to %02x\n", port, value);
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}
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};
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class AYPortHandler: public GI::AY38910::PortHandler {
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};
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@ -38,9 +31,11 @@ class ConcreteMachine:
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public:
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ConcreteMachine():
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z80_(*this),
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i8255_(i8255_port_handler_) {
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i8255_(i8255_port_handler_),
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i8255_port_handler_(*this) {
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ay_.set_port_handler(&ay_port_handler_);
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set_clock_rate(3579545);
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std::memset(unpopulated_, 0xff, sizeof(unpopulated_));
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}
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void setup_output(float aspect_ratio) override {
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@ -69,6 +64,28 @@ class ConcreteMachine:
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return true;
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}
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void page_memory(uint8_t value) {
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for(int c = 0; c < 4; ++c) {
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read_pointers_[c] = unpopulated_;
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write_pointers_[c] = scratch_;
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}
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switch(value&3) {
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case 0: read_pointers_[0] = main_.data(); break;
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case 2: read_pointers_[0] = write_pointers_[0] = &ram_[0]; break;
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}
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switch((value >> 2)&3) {
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case 0: read_pointers_[1] = basic_.data(); break;
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case 2: read_pointers_[1] = write_pointers_[1] = &ram_[16384]; break;
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}
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switch((value >> 4)&3) {
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case 2: read_pointers_[2] = write_pointers_[2] = &ram_[32768]; break;
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}
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switch((value >> 6)&3) {
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case 2: read_pointers_[3] = write_pointers_[3] = &ram_[49152]; break;
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}
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}
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HalfCycles perform_machine_cycle(const CPU::Z80::PartialMachineCycle &cycle) {
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uint16_t address = cycle.address ? *cycle.address : 0x0000;
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switch(cycle.operation) {
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@ -171,6 +188,31 @@ class ConcreteMachine:
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}
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private:
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class i8255PortHandler: public Intel::i8255::PortHandler {
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public:
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i8255PortHandler(ConcreteMachine &machine) : machine_(machine) {}
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void set_value(int port, uint8_t value) {
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switch(port) {
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case 0: machine_.page_memory(value); break;
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case 2:
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printf("?? Select keyboard row, etc: %02x\n", value);
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break;
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default: break;
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}
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}
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uint8_t get_value(int port) {
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if(port == 1) {
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printf("?? Read keyboard\n");
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}
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return 0xff;
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}
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private:
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ConcreteMachine &machine_;
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};
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CPU::Z80::Processor<ConcreteMachine, false, false> z80_;
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std::unique_ptr<TI::TMS9918> vdp_;
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Intel::i8255::i8255<i8255PortHandler> i8255_;
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@ -183,6 +225,7 @@ class ConcreteMachine:
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uint8_t *write_pointers_[4];
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uint8_t ram_[65536];
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uint8_t scratch_[16384];
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uint8_t unpopulated_[16384];
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std::vector<uint8_t> basic_, main_;
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HalfCycles time_since_vdp_update_;
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