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Attempt to round out addressing modes, shift to a header, as per templating on BusHandler.
This commit is contained in:
Thomas Harte
parent
0b19bbff8d
commit
6b073c6067
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@ -8,182 +8,3 @@
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#include "Executor.hpp"
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#include "Perform.hpp"
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#include <cassert>
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using namespace InstructionSet::M68k;
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template <Model model, typename BusHandler>
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Executor<model, BusHandler>::Executor(BusHandler &handler) : bus_handler_(handler) {
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reset();
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}
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::reset() {
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// Establish: supervisor state, all interrupts blocked.
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status_.set_status(0b0010'0011'1000'0000);
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// Seed stack pointer and program counter.
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data_[7] = bus_handler_.template read<uint32_t>(0);
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program_counter_.l = bus_handler_.template read<uint32_t>(4);
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}
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::read(DataSize size, uint32_t address, CPU::SlicedInt32 &value) {
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switch(size) {
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case DataSize::Byte:
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value.b = bus_handler_.template read<uint8_t>(address);
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break;
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case DataSize::Word:
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value.w = bus_handler_.template read<uint16_t>(address);
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break;
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case DataSize::LongWord:
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value.l = bus_handler_.template read<uint32_t>(address);
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break;
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}
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}
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::write(DataSize size, uint32_t address, CPU::SlicedInt32 value) {
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switch(size) {
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case DataSize::Byte:
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bus_handler_.template write<uint8_t>(address, value.b);
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break;
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case DataSize::Word:
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bus_handler_.template write<uint16_t>(address, value.w);
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break;
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case DataSize::LongWord:
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bus_handler_.template write<uint32_t>(address, value.l);
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break;
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}
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}
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template <Model model, typename BusHandler>
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typename Executor<model, BusHandler>::EffectiveAddress Executor<model, BusHandler>::calculate_effective_address(Preinstruction instruction, uint16_t opcode, int index) {
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EffectiveAddress ea;
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switch(instruction.mode(index)) {
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case AddressingMode::None:
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// Permit an uninitialised effective address to be returned;
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// this value shouldn't be used.
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break;
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//
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// Operands that don't have effective addresses, which are returned as values.
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//
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case AddressingMode::DataRegisterDirect:
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ea.value.l = data_[instruction.reg(index)];
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ea.is_address = false;
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break;
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case AddressingMode::AddressRegisterDirect:
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ea.value.l = address_[instruction.reg(index)];
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ea.is_address = false;
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break;
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case AddressingMode::Quick:
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ea.value.l = quick(instruction.operation, opcode);
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ea.is_address = false;
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break;
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case AddressingMode::ImmediateData:
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read(instruction.size(), program_counter_.l, ea.value.l);
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program_counter_.l += (instruction.size() == DataSize::LongWord) ? 4 : 2;
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ea.is_address = false;
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break;
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//
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// Operands that are effective addresses.
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//
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default:
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// TODO.
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assert(false);
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break;
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}
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return ea;
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}
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::run_for_instructions(int count) {
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while(count--) {
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// TODO: check interrupt level, trace flag.
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// Read the next instruction.
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const auto instruction_address = program_counter_.l;
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const uint16_t opcode = bus_handler_.template read<uint16_t>(program_counter_.l);
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const Preinstruction instruction = decoder_.decode(opcode);
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program_counter_.l += 2;
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// TODO: check privilege level.
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// Temporary storage.
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CPU::SlicedInt32 operand_[2];
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EffectiveAddress effective_address_[2];
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// Calculate effective addresses; copy 'addresses' into the
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// operands by default both: (i) because they might be values,
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// rather than addresses; and (ii) then they'll be there for use
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// by LEA and PEA.
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//
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// TODO: this work should be performed by a full Decoder, so that it can be cached.
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effective_address_[0] = calculate_effective_address(instruction, opcode, 0);
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effective_address_[1] = calculate_effective_address(instruction, opcode, 1);
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operand_[0] = effective_address_[0].value;
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operand_[1] = effective_address_[1].value;
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// Obtain the appropriate sequence.
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//
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// TODO: make a decision about whether this goes into a fully-decoded Instruction.
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Sequence<model> sequence(instruction.operation);
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// Perform it.
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while(!sequence.empty()) {
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const auto step = sequence.pop_front();
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switch(step) {
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default: assert(false); // i.e. TODO
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case Step::FetchOp1:
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case Step::FetchOp2: {
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const auto index = int(step) & 1;
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// If the operand wasn't indirect, it's already fetched.
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if(!effective_address_[index].is_address) continue;
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// TODO: potential bus alignment exception.
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read(instruction.size(), effective_address_[index].value, operand_[index]);
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} break;
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case Step::Perform:
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perform<model>(instruction, operand_[0], operand_[1], status_, this);
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break;
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case Step::StoreOp1:
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case Step::StoreOp2: {
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const auto index = int(step) & 1;
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// If the operand wasn't indirect, it's already fetched.
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if(!effective_address_[index].is_address) {
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// This must be either address or data register indirect.
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assert(
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instruction.mode(index) == AddressingMode::DataRegisterDirect ||
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instruction.mode(index) == AddressingMode::AddressRegisterDirect);
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// TODO: is it worth holding registers as a single block to avoid this conditional?
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if(instruction.mode(index) == AddressingMode::DataRegisterDirect) {
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data_[instruction.reg(index)] = operand_[index];
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} else {
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address_[instruction.reg(index)] = operand_[index];
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}
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break;
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}
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// TODO: potential bus alignment exception.
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write(instruction.size(), effective_address_[index].value, operand_[index]);
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} break;
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}
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}
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}
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}
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@ -50,15 +50,26 @@ template <Model model, typename BusHandler> class Executor {
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void read(DataSize size, uint32_t address, CPU::SlicedInt32 &value);
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void write(DataSize size, uint32_t address, CPU::SlicedInt32 value);
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template <typename IntT> IntT read_pc();
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uint32_t index_8bitdisplacement();
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// Processor state.
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Status status_;
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CPU::SlicedInt32 program_counter_;
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CPU::SlicedInt32 data_[8], address_[8];
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CPU::SlicedInt32 stack_pointers_[2];
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uint32_t instruction_address_;
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// A lookup table to ensure that A7 is adjusted by 2 rather than 1 in
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// postincrement and predecrement mode.
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static constexpr uint32_t byte_increments[] = {
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1, 1, 1, 1, 1, 1, 1, 2
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};
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};
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}
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}
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#include "Implementation/ExecutorImplementation.hpp"
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#endif /* InstructionSets_M68k_Executor_hpp */
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282
InstructionSets/M68k/Implementation/ExecutorImplementation.hpp
Normal file
282
InstructionSets/M68k/Implementation/ExecutorImplementation.hpp
Normal file
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@ -0,0 +1,282 @@
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//
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// ExecutorImplementation.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 01/05/2022.
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// Copyright © 2022 Thomas Harte. All rights reserved.
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//
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#ifndef InstructionSets_M68k_ExecutorImplementation_hpp
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#define InstructionSets_M68k_ExecutorImplementation_hpp
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#include "Perform.hpp"
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#include <cassert>
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namespace InstructionSet {
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namespace M68k {
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template <Model model, typename BusHandler>
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Executor<model, BusHandler>::Executor(BusHandler &handler) : bus_handler_(handler) {
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reset();
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}
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::reset() {
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// Establish: supervisor state, all interrupts blocked.
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status_.set_status(0b0010'0011'1000'0000);
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// Seed stack pointer and program counter.
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data_[7] = bus_handler_.template read<uint32_t>(0);
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program_counter_.l = bus_handler_.template read<uint32_t>(4);
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}
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::read(DataSize size, uint32_t address, CPU::SlicedInt32 &value) {
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switch(size) {
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case DataSize::Byte:
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value.b = bus_handler_.template read<uint8_t>(address);
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break;
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case DataSize::Word:
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value.w = bus_handler_.template read<uint16_t>(address);
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break;
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case DataSize::LongWord:
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value.l = bus_handler_.template read<uint32_t>(address);
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break;
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}
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}
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::write(DataSize size, uint32_t address, CPU::SlicedInt32 value) {
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switch(size) {
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case DataSize::Byte:
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bus_handler_.template write<uint8_t>(address, value.b);
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break;
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case DataSize::Word:
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bus_handler_.template write<uint16_t>(address, value.w);
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break;
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case DataSize::LongWord:
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bus_handler_.template write<uint32_t>(address, value.l);
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break;
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}
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}
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template <Model model, typename BusHandler>
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template <typename IntT> IntT Executor<model, BusHandler>::read_pc() {
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const IntT result = bus_handler_.template read<IntT>(program_counter_.l);
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if constexpr (sizeof(IntT) == 4) {
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program_counter_.l += 4;
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} else {
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program_counter_.l += 2;
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}
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return result;
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}
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template <Model model, typename BusHandler>
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uint32_t Executor<model, BusHandler>::index_8bitdisplacement() {
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// TODO: if not a 68000, check bit 8 for whether this should be a full extension word;
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// also include the scale field even if not.
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const auto extension = read_pc<uint16_t>();
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const auto offset = int8_t(extension);
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const int register_index = (extension >> 11) & 7;
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const uint32_t displacement = (extension & 0x8000) ? address_[register_index].l : data_[register_index].l;
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return offset + (extension & 0x800) ? displacement : uint16_t(displacement);
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}
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template <Model model, typename BusHandler>
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typename Executor<model, BusHandler>::EffectiveAddress Executor<model, BusHandler>::calculate_effective_address(Preinstruction instruction, uint16_t opcode, int index) {
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EffectiveAddress ea;
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switch(instruction.mode(index)) {
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case AddressingMode::None:
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// Permit an uninitialised effective address to be returned;
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// this value shouldn't be used.
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break;
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//
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// Operands that don't have effective addresses, which are returned as values.
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//
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case AddressingMode::DataRegisterDirect:
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ea.value.l = data_[instruction.reg(index)];
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ea.is_address = false;
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break;
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case AddressingMode::AddressRegisterDirect:
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ea.value.l = address_[instruction.reg(index)];
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ea.is_address = false;
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break;
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case AddressingMode::Quick:
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ea.value.l = quick(instruction.operation, opcode);
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ea.is_address = false;
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break;
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case AddressingMode::ImmediateData:
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read(instruction.size(), program_counter_.l, ea.value.l);
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program_counter_.l += (instruction.size() == DataSize::LongWord) ? 4 : 2;
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ea.is_address = false;
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break;
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//
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// Absolute addresses.
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//
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case AddressingMode::AbsoluteShort:
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ea.value.l = int16_t(read_pc<uint16_t>());
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ea.is_address = true;
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break;
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case AddressingMode::AbsoluteLong:
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ea.value.l = read_pc<uint32_t>();
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ea.is_address = true;
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break;
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//
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// Address register indirects.
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//
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case AddressingMode::AddressRegisterIndirect:
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ea.value.l = address_[instruction.reg(index)];
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ea.is_address = true;
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break;
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case AddressingMode::AddressRegisterIndirectWithPostincrement: {
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const auto reg = instruction.reg(index);
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ea.value.l = address_[reg];
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ea.is_address = true;
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switch(instruction.size()) {
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case DataSize::Byte: address_[reg] += byte_increments[reg]; break;
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case DataSize::Word: address_[reg] += 2; break;
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case DataSize::LongWord: address_[reg] += 4; break;
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}
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} break;
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case AddressingMode::AddressRegisterIndirectWithPredecrement: {
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const auto reg = instruction.reg(index);
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switch(instruction.size()) {
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case DataSize::Byte: address_[reg] -= byte_increments[reg]; break;
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case DataSize::Word: address_[reg] -= 2; break;
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case DataSize::LongWord: address_[reg] -= 4; break;
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}
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ea.value.l = address_[reg];
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ea.is_address = true;
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} break;
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case AddressingMode::AddressRegisterIndirectWithDisplacement:
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ea.value.l = address_[instruction.reg(index)] + int16_t(read_pc<uint16_t>());
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ea.is_address = true;
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break;
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case AddressingMode::AddressRegisterIndirectWithIndex8bitDisplacement:
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ea.value.l = address_[instruction.reg(index)] + index_8bitdisplacement();
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ea.is_address = true;
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break;
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//
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// PC-relative addresses.
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//
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// TODO: rephrase these in terms of instruction_address_. Just for security
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// against whatever mutations the PC has been through already to get to here.
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//
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case AddressingMode::ProgramCounterIndirectWithDisplacement:
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ea.value.l = program_counter_.l + int16_t(read_pc<uint16_t>());
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ea.is_address = true;
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break;
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case AddressingMode::ProgramCounterIndirectWithIndex8bitDisplacement:
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ea.value.l = program_counter_.l + index_8bitdisplacement();
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ea.is_address = true;
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break;
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default:
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// TODO.
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assert(false);
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break;
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}
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return ea;
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}
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template <Model model, typename BusHandler>
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void Executor<model, BusHandler>::run_for_instructions(int count) {
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while(count--) {
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// TODO: check interrupt level, trace flag.
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// Read the next instruction.
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instruction_address_ = program_counter_.l;
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const auto opcode = read_pc<uint16_t>();
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const Preinstruction instruction = decoder_.decode(opcode);
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program_counter_.l += 2;
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// TODO: check privilege level.
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// Temporary storage.
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CPU::SlicedInt32 operand_[2];
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EffectiveAddress effective_address_[2];
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// Calculate effective addresses; copy 'addresses' into the
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// operands by default both: (i) because they might be values,
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// rather than addresses; and (ii) then they'll be there for use
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// by LEA and PEA.
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//
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// TODO: this work should be performed by a full Decoder, so that it can be cached.
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effective_address_[0] = calculate_effective_address(instruction, opcode, 0);
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effective_address_[1] = calculate_effective_address(instruction, opcode, 1);
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operand_[0] = effective_address_[0].value;
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operand_[1] = effective_address_[1].value;
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// Obtain the appropriate sequence.
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//
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// TODO: make a decision about whether this goes into a fully-decoded Instruction.
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Sequence<model> sequence(instruction.operation);
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// Perform it.
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while(!sequence.empty()) {
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const auto step = sequence.pop_front();
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switch(step) {
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default: assert(false); // i.e. TODO
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case Step::FetchOp1:
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case Step::FetchOp2: {
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const auto index = int(step) & 1;
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// If the operand wasn't indirect, it's already fetched.
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if(!effective_address_[index].is_address) continue;
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// TODO: potential bus alignment exception.
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read(instruction.size(), effective_address_[index].value, operand_[index]);
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} break;
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case Step::Perform:
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perform<model>(instruction, operand_[0], operand_[1], status_, this);
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break;
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case Step::StoreOp1:
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case Step::StoreOp2: {
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const auto index = int(step) & 1;
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// If the operand wasn't indirect, it's already fetched.
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if(!effective_address_[index].is_address) {
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// This must be either address or data register indirect.
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assert(
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instruction.mode(index) == AddressingMode::DataRegisterDirect ||
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instruction.mode(index) == AddressingMode::AddressRegisterDirect);
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// TODO: is it worth holding registers as a single block to avoid this conditional?
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if(instruction.mode(index) == AddressingMode::DataRegisterDirect) {
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data_[instruction.reg(index)] = operand_[index];
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} else {
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address_[instruction.reg(index)] = operand_[index];
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}
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break;
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}
|
||||
|
||||
// TODO: potential bus alignment exception.
|
||||
write(instruction.size(), effective_address_[index].value, operand_[index]);
|
||||
} break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* InstructionSets_M68k_ExecutorImplementation_hpp */
|
||||
|
|
@ -303,23 +303,23 @@ enum class AddressingMode: uint8_t {
|
|||
AddressRegisterIndirectWithDisplacement = 0b00'101,
|
||||
/// (d8, An, Xn)
|
||||
AddressRegisterIndirectWithIndex8bitDisplacement = 0b00'110,
|
||||
/// (bd, An, Xn)
|
||||
/// (bd, An, Xn) [68020+]
|
||||
AddressRegisterIndirectWithIndexBaseDisplacement = 0b10'000,
|
||||
|
||||
/// ([bd, An, Xn], od)
|
||||
/// ([bd, An, Xn], od) [68020+]
|
||||
MemoryIndirectPostindexed = 0b10'001,
|
||||
/// ([bd, An], Xn, od)
|
||||
/// ([bd, An], Xn, od) [68020+]
|
||||
MemoryIndirectPreindexed = 0b10'010,
|
||||
|
||||
/// (d16, PC)
|
||||
ProgramCounterIndirectWithDisplacement = 0b01'010,
|
||||
/// (d8, PC, Xn)
|
||||
ProgramCounterIndirectWithIndex8bitDisplacement = 0b01'011,
|
||||
/// (bd, PC, Xn)
|
||||
/// (bd, PC, Xn) [68020+]
|
||||
ProgramCounterIndirectWithIndexBaseDisplacement = 0b10'011,
|
||||
/// ([bd, PC, Xn], od)
|
||||
/// ([bd, PC, Xn], od) [68020+]
|
||||
ProgramCounterMemoryIndirectPostindexed = 0b10'100,
|
||||
/// ([bc, PC], Xn, od)
|
||||
/// ([bc, PC], Xn, od) [68020+]
|
||||
ProgramCounterMemoryIndirectPreindexed = 0b10'101,
|
||||
|
||||
/// (xxx).W
|
||||
|
|
|
|||
|
|
@ -1943,6 +1943,7 @@
|
|||
4BB5B99A281B244400522DA9 /* PerformImplementation.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = PerformImplementation.hpp; sourceTree = "<group>"; };
|
||||
4BB5B99B281C805300522DA9 /* Executor.cpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.cpp; path = Executor.cpp; sourceTree = "<group>"; };
|
||||
4BB5B99C281C805300522DA9 /* Executor.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = Executor.hpp; sourceTree = "<group>"; };
|
||||
4BB5B99F281F121200522DA9 /* ExecutorImplementation.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = ExecutorImplementation.hpp; sourceTree = "<group>"; };
|
||||
4BB697C91D4B6D3E00248BDF /* TimedEventLoop.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = TimedEventLoop.cpp; sourceTree = "<group>"; };
|
||||
4BB697CA1D4B6D3E00248BDF /* TimedEventLoop.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = TimedEventLoop.hpp; sourceTree = "<group>"; };
|
||||
4BB697CC1D4BA44400248BDF /* CommodoreGCR.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = CommodoreGCR.cpp; path = Encodings/CommodoreGCR.cpp; sourceTree = "<group>"; };
|
||||
|
|
@ -4092,6 +4093,7 @@
|
|||
isa = PBXGroup;
|
||||
children = (
|
||||
4BB5B99A281B244400522DA9 /* PerformImplementation.hpp */,
|
||||
4BB5B99F281F121200522DA9 /* ExecutorImplementation.hpp */,
|
||||
);
|
||||
path = Implementation;
|
||||
sourceTree = "<group>";
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user