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Adjust my expectation as to length.
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2bd20446bb
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@ -870,7 +870,16 @@
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XCTAssertEqual(state.registers.data[1], 0x1fffffff);
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XCTAssertEqual(state.registers.data[1], 0x1fffffff);
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XCTAssertEqual(state.registers.supervisor_stack_pointer, initial_sp - 6);
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XCTAssertEqual(state.registers.supervisor_stack_pointer, initial_sp - 6);
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XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
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XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
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XCTAssertEqual(44, self.machine->get_cycle_count());
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// Total expected bus pattern:
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//
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// np | nn nn | nw nw nw np np np n np = 42 cycles
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//
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// Noted: Yacht shows a total of three nps for a DIVS #;
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// I believe this is incorrect as it includes two in the
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// '1st op (ea)' stage, but an immediate word causes
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// only one elsewhere.
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XCTAssertEqual(42, self.machine->get_cycle_count());
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// Check stack contents; should be PC.l, PC.h and status register.
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// Check stack contents; should be PC.l, PC.h and status register.
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// Assumed: the program counter on the stack is that of the
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// Assumed: the program counter on the stack is that of the
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