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Fix bus/address error exception frame: order and contents.
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Thomas Harte
parent
10b9b13673
commit
6fcaf3571e
@ -328,6 +328,12 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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exception_vector_ = x; \
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MoveToStateSpecific(StandardException);
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// Copies the current program counter, adjusted to allow for the prefetch queue,
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// into the instruction_address_ latch, which is the source of the value written
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// during exceptions.
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#define ReloadInstructionAddress() \
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instruction_address_.l = program_counter_.l - 4
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using Mode = InstructionSet::M68k::AddressingMode;
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// Otherwise continue for all time, until back in debt.
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@ -429,11 +435,11 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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// So the below is a cross-your-fingers guess based on the constraints
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// that the information writen, from lowest address to highest is:
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//
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// R/W, I/N, function code word; [at -2]
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// access address; [-6]
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// R/W, I/N, function code word; [at -14]
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// access address; [-12]
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// instruction register; [-8]
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// status register; [-10]
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// program counter. [-14]
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// status register; [-6]
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// program counter. [-4]
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//
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// With the instruction register definitely being written before the
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// function code word.
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@ -444,11 +450,12 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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//
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// So, based on the hoopy ordering of a standard exception, maybe:
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//
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// 1) status register;
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// 2) program counter;
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// 3) instruction register;
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// 4) function code;
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// 5) access address?
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// 1) program counter low;
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// 2) captured state;
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// 3) program counter high;
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// 4) instruction register;
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// 5) function code;
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// 6) access address?
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IdleBus(2);
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@ -460,33 +467,49 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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SetupDataAccess(0, Microcycle::SelectWord);
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SetDataAddress(registers_[15].l);
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registers_[15].l -= 10;
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Access(captured_status_); // ns
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temporary_address_.l = program_counter_.l;
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// Guess: the written program counter is adjusted to discount the prefetch queue.
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// COMPLETE GUESS.
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temporary_address_.l = program_counter_.l - 4;
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registers_[15].l -= 2;
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Access(temporary_address_.low); // ns
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Access(temporary_address_.low); // ns [pc.l]
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registers_[15].l -= 2;
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Access(temporary_address_.high); // nS
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registers_[15].l -= 4;
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Access(captured_status_); // ns [sr]
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registers_[15].l += 6;
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registers_[15].l += 2;
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Access(temporary_address_.high); // nS [pc.h]
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registers_[15].l -= 4;
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temporary_value_.w = opcode_;
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Access(temporary_value_.low); // ns
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Access(temporary_value_.low); // ns [instruction register]
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// TODO: construct the function code.
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temporary_value_.w = (temporary_value_.w & ~31);
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// Construct the function code; which is:
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//
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// b4: 1 = was a read; 0 = was a write;
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// b3: 0 = was reading an instruction; 1 = wasn't;
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// b2–b0: the regular 68000 function code;
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// [all other bits]: left over from the instruction register write, above.
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//
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// I'm unable to come up with a reason why the function code isn't duplicative
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// of b3, but given the repetition of supervisor state which is also in the
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// captured status register I guess maybe it is just duplicative.
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temporary_value_.w =
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(temporary_value_.w & ~31) |
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((bus_error_.operation & Microcycle::Read) ? 0x10 : 0x00) |
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((bus_error_.operation & Microcycle::IsProgram) ? 0x08 : 0x00) |
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((bus_error_.operation & Microcycle::IsProgram) ? 0x02 : 0x01) |
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((captured_status_.w & InstructionSet::M68k::ConditionCode::Supervisor) ? 0x04 : 0x00);
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registers_[15].l += 6;
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Access(temporary_value_.low); // ns
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registers_[15].l -= 6;
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Access(temporary_value_.low); // ns [function code]
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temporary_address_.l = *bus_error_.address;
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registers_[15].l -= 2;
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Access(temporary_value_.low); // ns
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registers_[15].l += 4;
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Access(temporary_address_.low); // ns [error address.l]
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registers_[15].l -= 2;
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Access(temporary_value_.high); // nS
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registers_[15].l -= 8;
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Access(temporary_address_.high); // nS [error address.h]
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registers_[15].l -= 2;
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// Grab new program counter.
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SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
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@ -502,7 +525,6 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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Prefetch(); // np
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IdleBus(1); // n
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Prefetch(); // np
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MoveToStateSpecific(Decode);
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// Acknowledge an interrupt, thereby obtaining an exception vector,
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@ -521,7 +543,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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// Push low part of program counter.
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registers_[15].l -= 2;
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Access(instruction_address_.low); // ns
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Access(instruction_address_.low); // ns
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// Do the interrupt cycle, to obtain a vector.
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temporary_address_.l = 0xffff'fff1 | uint32_t(captured_interrupt_level_ << 1);
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@ -536,7 +558,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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// TODO: if bus error is set, treat interrupt as spurious.
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IdleBus(3); // n- n
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IdleBus(3); // n- n
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// Do the rest of the stack work.
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SetupDataAccess(0, Microcycle::SelectWord);
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@ -554,10 +576,10 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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SetDataAddress(temporary_address_.l);
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temporary_address_.l = uint32_t(temporary_value_.w << 2);
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Access(program_counter_.high); // nV
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Access(program_counter_.high); // nV
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temporary_address_.l += 2;
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Access(program_counter_.low); // nv
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Access(program_counter_.low); // nv
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// Populate the prefetch queue.
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Prefetch(); // np
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@ -571,7 +593,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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CheckOverrun();
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// Capture the address of the next instruction.
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instruction_address_.l = program_counter_.l - 4;
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ReloadInstructionAddress();
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// Head off into an interrupt if one is found.
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if(captured_interrupt_level_ > status_.interrupt_level) {
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@ -1771,12 +1793,12 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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BeginState(CHK_was_over):
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IdleBus(2); // nn
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instruction_address_.l = program_counter_.l - 4;
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ReloadInstructionAddress();
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RaiseException(InstructionSet::M68k::Exception::CHK);
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BeginState(CHK_was_under):
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IdleBus(3); // n nn
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instruction_address_.l = program_counter_.l - 4;
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ReloadInstructionAddress();
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RaiseException(InstructionSet::M68k::Exception::CHK);
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//
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@ -2485,6 +2507,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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#undef CheckOverrun
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#undef Spend
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#undef ConsiderExit
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#undef ReloadInstructionAddress
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}
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