diff --git a/OSBindings/Mac/Clock SignalTests/68000Tests.mm b/OSBindings/Mac/Clock SignalTests/68000Tests.mm
index 64a5e60a4..14292828a 100644
--- a/OSBindings/Mac/Clock SignalTests/68000Tests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/68000Tests.mm	
@@ -1651,6 +1651,91 @@ class CPU::MC68000::ProcessorStorageTests {
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
+// MARK: ROL
+
+- (void)testROLb_8 {
+	_machine->set_program({
+		0xe118		// ROL.B #8, D0
+	});
+	auto state = _machine->get_processor_state();
+	state.data[0] = 0xce3dd567;
+
+	_machine->set_processor_state(state);
+	_machine->run_for_instructions(1);
+
+	state = _machine->get_processor_state();
+	XCTAssertEqual(state.data[0], 0xce3dd567);
+	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry);
+	XCTAssertEqual(22, _machine->get_cycle_count());
+}
+
+- (void)testROLb_1 {
+	_machine->set_program({
+		0xe318		// ROL.B #1, D0
+	});
+	auto state = _machine->get_processor_state();
+	state.data[0] = 0xce3dd567;
+
+	_machine->set_processor_state(state);
+	_machine->run_for_instructions(1);
+
+	state = _machine->get_processor_state();
+	XCTAssertEqual(state.data[0], 0xce3dd5ce);
+	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(8, _machine->get_cycle_count());
+}
+
+- (void)testROLb_2 {
+	_machine->set_program({
+		0xe518		// ROL.B #2, D0
+	});
+	auto state = _machine->get_processor_state();
+	state.data[0] = 0xce3dd567;
+	state.status = Flag::ConditionCodes;
+
+	_machine->set_processor_state(state);
+	_machine->run_for_instructions(1);
+
+	state = _machine->get_processor_state();
+	XCTAssertEqual(state.data[0], 0xce3dd59d);
+	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Extend | Flag::Carry);
+	XCTAssertEqual(10, _machine->get_cycle_count());
+}
+
+- (void)testROLb_7 {
+	_machine->set_program({
+		0xef18		// ROL.B #7, D0
+	});
+	auto state = _machine->get_processor_state();
+	state.data[0] = 0xce3dd567;
+	state.status = Flag::ConditionCodes;
+
+	_machine->set_processor_state(state);
+	_machine->run_for_instructions(1);
+
+	state = _machine->get_processor_state();
+	XCTAssertEqual(state.data[0], 0xce3dd5b3);
+	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Extend | Flag::Carry);
+	XCTAssertEqual(20, _machine->get_cycle_count());
+}
+
+- (void)testROLw_8 {
+	_machine->set_program({
+		0xe158		// ROL.w #7, D0
+	});
+	auto state = _machine->get_processor_state();
+	state.data[0] = 0xce3dd567;
+	state.status = Flag::ConditionCodes;
+
+	_machine->set_processor_state(state);
+	_machine->run_for_instructions(1);
+
+	state = _machine->get_processor_state();
+	XCTAssertEqual(state.data[0], 0xce3d67d5);
+	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	XCTAssertEqual(22, _machine->get_cycle_count());
+}
+
 // MARK: Scc
 
 - (void)testSFDn {
diff --git a/Processors/68000/Implementation/68000Implementation.hpp b/Processors/68000/Implementation/68000Implementation.hpp
index a3f79e90c..c75c797e6 100644
--- a/Processors/68000/Implementation/68000Implementation.hpp
+++ b/Processors/68000/Implementation/68000Implementation.hpp
@@ -1538,7 +1538,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
 
 #define decode_shift_count()	\
 	int shift_count = (decoded_instruction_.full & 32) ? data_[(decoded_instruction_.full >> 9) & 7].full&63 : ( ((decoded_instruction_.full >> 9)&7) ? ((decoded_instruction_.full >> 9)&7) : 8) ;	\
-	active_step_->microcycle.length = HalfCycles(4 * shift_count);
+	bus_program->microcycle.length = HalfCycles(4 * shift_count);
 
 #define set_flags_b(t) set_flags(active_program_->destination->halves.low.halves.low, 0x80, t)
 #define set_flags_w(t) set_flags(active_program_->destination->halves.low.full, 0x8000, t)