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Implements 80 and 81.

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This commit is contained in:
Thomas Harte 2021-01-08 22:50:59 -05:00
parent 68fe16a092
commit 718f950071
2 changed files with 27 additions and 2 deletions
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23
Processors/Decoders/x86/x86.cpp
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@ -165,8 +165,11 @@ std::pair<int, Instruction> Decoder::decode(const uint8_t *source, size_t length
// TODO:
//
// 0x80, 0x81, 0x82, 0x83, which all require more
// input, from the ModRegRM byte.
// 0x82, 0x83, which will require me to do something
// re: word-sign extended.
case 0x80: MemRegReg(Invalid, MemRegADD_to_CMP, 1); break;
case 0x81: MemRegReg(Invalid, MemRegADD_to_CMP, 2); break;
case 0x84: MemRegReg(TEST, MemReg_Reg, 1); break;
case 0x85: MemRegReg(TEST, MemReg_Reg, 2); break;
@ -503,6 +506,22 @@ std::pair<int, Instruction> Decoder::decode(const uint8_t *source, size_t length
operand_size_ = operation_size_;
break;
case ModRegRMFormat::MemRegADD_to_CMP:
destination_ = memreg;
operand_size_ = operation_size_;
switch(reg) {
default: operation_ = Operation::ADD; break;
case 1: operation_ = Operation::OR; break;
case 2: operation_ = Operation::ADC; break;
case 3: operation_ = Operation::SBB; break;
case 4: operation_ = Operation::AND; break;
case 5: operation_ = Operation::SUB; break;
case 6: operation_ = Operation::XOR; break;
case 7: operation_ = Operation::CMP; break;
}
break;
default: assert(false);
}

6
Processors/Decoders/x86/x86.hpp
View File

@ -238,6 +238,12 @@ struct Decoder {
// to pick an operation from the ROL/ROR/RCL/RCR/SAL/SHR/SAR group.
MemRegROL_to_SAR,
// Parse for mode and register/memory fields, populating the
// destination_ field with the result. Use the 'register' field
// to pick an operation from the ADD/OR/ADC/SBB/AND/SUB/XOR/CMP group and
// waits for an operand equal to the operation size.
MemRegADD_to_CMP,
// Parse for mode and register/memory fields, populating the
// source_ field with the result. Fills destination_ with a segment
// register based on the reg field.