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mirror of https://github.com/TomHarte/CLK.git synced 2024-06-25 18:30:07 +00:00

Factored out the stuff that both all-RAM processors would share, rather than duplicating it.

This commit is contained in:
Thomas Harte 2017-05-16 21:28:17 -04:00
parent d559d8b901
commit 7190f927b7
7 changed files with 72 additions and 38 deletions

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@ -412,6 +412,7 @@
4BF829631D8F536B001BAE39 /* SSD.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BF829611D8F536B001BAE39 /* SSD.cpp */; };
4BF829661D8F732B001BAE39 /* Disk.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BF829641D8F732B001BAE39 /* Disk.cpp */; };
4BFCA1201ECBDC1500AC40C1 /* Z80AllRAM.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BFCA11D1ECBD9BD00AC40C1 /* Z80AllRAM.cpp */; };
4BFCA1241ECBDCB400AC40C1 /* AllRAMProcessor.cpp in Sources */ = {isa = PBXBuildFile; fileRef = 4BFCA1211ECBDCAF00AC40C1 /* AllRAMProcessor.cpp */; };
/* End PBXBuildFile section */
/* Begin PBXContainerItemProxy section */
@ -975,6 +976,8 @@
4BF829681D8F7361001BAE39 /* File.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; name = File.hpp; path = ../../StaticAnalyser/Acorn/File.hpp; sourceTree = "<group>"; };
4BFCA11D1ECBD9BD00AC40C1 /* Z80AllRAM.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = Z80AllRAM.cpp; path = Z80/Z80AllRAM.cpp; sourceTree = "<group>"; };
4BFCA11E1ECBD9BD00AC40C1 /* Z80AllRAM.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; name = Z80AllRAM.hpp; path = Z80/Z80AllRAM.hpp; sourceTree = "<group>"; };
4BFCA1211ECBDCAF00AC40C1 /* AllRAMProcessor.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = AllRAMProcessor.cpp; sourceTree = "<group>"; };
4BFCA1221ECBDCAF00AC40C1 /* AllRAMProcessor.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = AllRAMProcessor.hpp; sourceTree = "<group>"; };
/* End PBXFileReference section */
/* Begin PBXFrameworksBuildPhase section */
@ -1813,6 +1816,8 @@
4B77069E1EC9045B0053B588 /* Z80 */,
4B7706A01EC9398D0053B588 /* MicroOpScheduler.hpp */,
4B2C455C1EC9442600FC74DD /* RegisterSizes.hpp */,
4BFCA1211ECBDCAF00AC40C1 /* AllRAMProcessor.cpp */,
4BFCA1221ECBDCAF00AC40C1 /* AllRAMProcessor.hpp */,
);
name = Processors;
path = ../../Processors;
@ -2551,6 +2556,7 @@
4BC9E1EE1D23449A003FCEE4 /* 6502InterruptTests.swift in Sources */,
4BEF6AAA1D35CE9E00E73575 /* DigitalPhaseLockedLoopBridge.mm in Sources */,
4B924E991E74D22700B76AF1 /* AtariStaticAnalyserTests.mm in Sources */,
4BFCA1241ECBDCB400AC40C1 /* AllRAMProcessor.cpp in Sources */,
4B50730A1DDFCFDF00C48FBD /* ArrayBuilderTests.mm in Sources */,
4B2AF8691E513FC20027EE29 /* TIATests.mm in Sources */,
4B3BA0CE1D318B44005DD7A7 /* C1540Bridge.mm in Sources */,

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@ -12,9 +12,7 @@
using namespace CPU::MOS6502;
AllRAMProcessor::AllRAMProcessor() : _timestamp(0) {
set_power_on(false);
}
AllRAMProcessor::AllRAMProcessor() : ::CPU::AllRAMProcessor(65536) {}
int AllRAMProcessor::perform_bus_operation(MOS6502::BusOperation operation, uint16_t address, uint8_t *value) {
timestamp_++;
@ -27,12 +25,3 @@ int AllRAMProcessor::perform_bus_operation(MOS6502::BusOperation operation, uint
return 1;
}
void AllRAMProcessor::set_data_at_address(uint16_t startAddress, size_t length, const uint8_t *data) {
size_t endAddress = std::min(startAddress + length, (size_t)65536);
memcpy(&memory_[startAddress], data, endAddress - startAddress);
}
uint32_t AllRAMProcessor::get_timestamp() {
return timestamp_;
}

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@ -10,22 +10,19 @@
#define MOS6502AllRAM_cpp
#include "6502.hpp"
#include "../AllRAMProcessor.hpp"
namespace CPU {
namespace MOS6502 {
class AllRAMProcessor: public Processor<AllRAMProcessor> {
class AllRAMProcessor:
public ::CPU::AllRAMProcessor,
public Processor<AllRAMProcessor> {
public:
AllRAMProcessor();
int perform_bus_operation(MOS6502::BusOperation operation, uint16_t address, uint8_t *value);
void set_data_at_address(uint16_t startAddress, size_t length, const uint8_t *data);
uint32_t get_timestamp();
private:
uint8_t memory_[65536];
uint32_t timestamp_;
};
}

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@ -0,0 +1,24 @@
//
// AllRAMProcessor.cpp
// Clock Signal
//
// Created by Thomas Harte on 16/05/2017.
// Copyright © 2017 Thomas Harte. All rights reserved.
//
#include "AllRAMProcessor.hpp"
using namespace CPU;
AllRAMProcessor::AllRAMProcessor(size_t memory_size) :
memory_(memory_size),
timestamp_(0) {}
void AllRAMProcessor::set_data_at_address(uint16_t startAddress, size_t length, const uint8_t *data) {
size_t endAddress = std::min(startAddress + length, (size_t)65536);
memcpy(&memory_[startAddress], data, endAddress - startAddress);
}
uint32_t AllRAMProcessor::get_timestamp() {
return timestamp_;
}

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@ -0,0 +1,30 @@
//
// AllRAMProcessor.hpp
// Clock Signal
//
// Created by Thomas Harte on 16/05/2017.
// Copyright © 2017 Thomas Harte. All rights reserved.
//
#ifndef AllRAMProcessor_hpp
#define AllRAMProcessor_hpp
#include <cstdint>
#include <vector>
namespace CPU {
class AllRAMProcessor {
public:
AllRAMProcessor(size_t memory_size);
uint32_t get_timestamp();
void set_data_at_address(uint16_t startAddress, size_t length, const uint8_t *data);
protected:
std::vector<uint8_t> memory_;
uint32_t timestamp_;
};
}
#endif /* AllRAMProcessor_hpp */

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@ -11,17 +11,8 @@
using namespace CPU::Z80;
AllRAMProcessor::AllRAMProcessor() {}
AllRAMProcessor::AllRAMProcessor() : ::CPU::AllRAMProcessor(65536) {}
int AllRAMProcessor::perform_machine_cycle(const MachineCycle *cycle) {
return 0;
}
void AllRAMProcessor::set_data_at_address(uint16_t startAddress, size_t length, const uint8_t *data) {
size_t endAddress = std::min(startAddress + length, (size_t)65536);
memcpy(&memory_[startAddress], data, endAddress - startAddress);
}
uint32_t AllRAMProcessor::get_timestamp() {
return timestamp_;
}

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@ -10,22 +10,19 @@
#define Z80AllRAM_hpp
#include "Z80.hpp"
#include "../AllRAMProcessor.hpp"
namespace CPU {
namespace Z80 {
class AllRAMProcessor: public Processor<AllRAMProcessor> {
class AllRAMProcessor:
public ::CPU::AllRAMProcessor,
public Processor<AllRAMProcessor> {
public:
AllRAMProcessor();
int perform_machine_cycle(const MachineCycle *cycle);
void set_data_at_address(uint16_t startAddress, size_t length, const uint8_t *data);
uint32_t get_timestamp();
private:
uint8_t memory_[65536];
uint32_t timestamp_;
};
}