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Immediately runs afoul of a read/write difference in the specs between 8/16-bit mode that suggests maybe this isn't a good structure.

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Perhaps generators of some sort?
This commit is contained in:
Thomas Harte 2020-09-23 22:28:15 -04:00
parent f9045b5352
commit 72b5584042
2 changed files with 15 additions and 0 deletions
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13
Processors/65816/Implementation/65816Storage.cpp
View File

@ -62,6 +62,19 @@ ProcessorStorage::ProcessorStorage() {
OperationMoveToNextProgram
});
// 1d. Absolute read-modify-write.
// const auto absolute_rmw =
// install_ops({
// CycleFetchIncrementPC, // OpCode.
// CycleFetchIncrementPC, // AAL.
// CycleFetchIncrementPC, // AAH.
// CycleFetchIncrementData, // Data low.
// OperationSkipIf8, // (don't do the next fetch if in emulation mode)
// CycleFetchIncrementData, // Data high.
// OperationPerform, // (whatever the operation is)
// OperationMoveToNextProgram
// });
// Install the instructions.
#define op set_instruction
/* 0x00 BRK s */

2
Processors/65816/Implementation/65816Storage.hpp
View File

@ -23,6 +23,8 @@ class ProcessorStorage {
CycleFetchIncrementData,
/// Stores a byte to the data address from the data buffer and increments the data address.
CycleStoreIncrementData,
/// Decrements the data address and writes a byte to it.
CycleDecrementStoreData,
/// Pushes a single byte from the data buffer to the stack.
CyclePush,