Further qmake warning corrections.

Components/5380/ncr5380.cpp

@@ -18,6 +18,11 @@ NCR5380::NCR5380(SCSI::Bus &bus, int clock_rate) :
 	clock_rate_(clock_rate) {
 	device_id_ = bus_.add_device();
 	bus_.add_observer(this);
+
+	// TODO: use clock rate and expected phase. This implementation currently
+	// provides only CPU-driven polling behaviour.
+	(void)clock_rate_;
+	(void)expected_phase_;
 }
 
 void NCR5380::write(int address, uint8_t value, bool) {

Components/8272/i8272.cpp

@@ -80,6 +80,10 @@ i8272::i8272(BusHandler &bus_handler, Cycles clock_rate) :
 	Storage::Disk::MFMController(clock_rate),
 	bus_handler_(bus_handler) {
 	posit_event(int(Event8272::CommandByte));
+
+	// TODO: implement DMA, etc. I have a vague intention to implement the IBM PC
+	// one day, that should help to force that stuff.
+	(void)bus_handler_;
 }
 
 ClockingHint::Preference i8272::preferred_clocking() const {

Components/8272/i8272.hpp

@@ -46,8 +46,8 @@ class i8272 : public Storage::Disk::MFMController {
 		virtual void select_drive(int number) = 0;
 
 	private:
-		// The bus handler, for interrupt and DMA-driven usage.
-		BusHandler &bus_handler_;
+		// The bus handler, for interrupt and DMA-driven usage. [TODO]
+        BusHandler &bus_handler_;
 		std::unique_ptr<BusHandler> allocated_bus_handler_;
 
 		// Status registers.

Components/DiskII/IWM.hpp

@@ -82,8 +82,9 @@ class IWM:
 
 		uint8_t data_register_ = 0;
 		uint8_t mode_ = 0;
-		bool read_write_ready_ = true;
-		bool write_overran_ = false;
+		// These related to functionality not-yet implemented.
+		// bool read_write_ready_ = true;
+		// bool write_overran_ = false;
 
 		int state_ = 0;