6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-07-06 01:28:57 +00:00
Code Issues Projects Releases Wiki Activity

Corrects now-unimplemented ADD/SUB.

Browse Source
This commit is contained in:
Thomas Harte 2019-04-03 19:43:54 -04:00
parent 689ba1d4a2
commit 73e1c8c780
2 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
OSBindings/Mac/Clock SignalTests/EmuTOSTests.mm
View File

@ -92,7 +92,7 @@ class EmuTOS: public CPU::MC68000::BusHandler {
// Put teardown code here. This method is called after the invocation of each test method in the class. // Put teardown code here. This method is called after the invocation of each test method in the class.
} }
- (void)testExample { - (void)testStartup {
// This is an example of a functional test case. // This is an example of a functional test case.
// Use XCTAssert and related functions to verify your tests produce the correct results. // Use XCTAssert and related functions to verify your tests produce the correct results.
_machine->run_for(HalfCycles(4000)); _machine->run_for(HalfCycles(4000));

6
Processors/68000/Implementation/68000Storage.cpp
View File

@ -502,7 +502,7 @@ struct ProcessorStorageConstructor {
// if(mode == 0x03) { // if(mode == 0x03) {
// op(int(Action::Increment4) | MicroOp::DestinationMask); // op(int(Action::Increment4) | MicroOp::DestinationMask);
// } // }
break; continue;
case 0x004: // ADD/SUB.bw Dn, -(An) case 0x004: // ADD/SUB.bw Dn, -(An)
// op( int(is_byte_access ? Action::Decrement1 : Action::Decrement2) | MicroOp::SourceMask, // op( int(is_byte_access ? Action::Decrement1 : Action::Decrement2) | MicroOp::SourceMask,
@ -859,7 +859,7 @@ struct ProcessorStorageConstructor {
default: // (An), (An)+, -(An), (d16, An), (d8, An Xn), (xxx).W, (xxx).L default: // (An), (An)+, -(An), (d16, An), (d8, An Xn), (xxx).W, (xxx).L
storage_.instructions[instruction].source = &storage_.source_bus_data_[0]; storage_.instructions[instruction].source = &storage_.source_bus_data_[0];
storage_.instructions[instruction].source_address = &storage_.source_bus_data_[source_register]; storage_.instructions[instruction].source_address = &storage_.address_[source_register];
break; break;
} }
@ -874,7 +874,7 @@ struct ProcessorStorageConstructor {
default: // (An), (An)+, -(An), (d16, An), (d8, An Xn), (xxx).W, (xxx).L default: // (An), (An)+, -(An), (d16, An), (d8, An Xn), (xxx).W, (xxx).L
storage_.instructions[instruction].destination = &storage_.destination_bus_data_[0]; storage_.instructions[instruction].destination = &storage_.destination_bus_data_[0];
storage_.instructions[instruction].destination = &storage_.source_bus_data_[destination_register]; storage_.instructions[instruction].destination = &storage_.address_[destination_register];
break; break;
} }