diff --git a/Processors/6502Esque/Implementation/LazyFlags.hpp b/Processors/6502Esque/Implementation/LazyFlags.hpp
index 47904a992..5f330ff0f 100644
--- a/Processors/6502Esque/Implementation/LazyFlags.hpp
+++ b/Processors/6502Esque/Implementation/LazyFlags.hpp
@@ -33,15 +33,22 @@ struct LazyFlags {
 	/// Contains Flag::Interrupt, complemented.
 	uint8_t inverse_interrupt = 0;
 
+	/// Sets N and Z flags per the 8-bit value @c value.
 	void set_nz(uint8_t value) {
 		zero_result = negative_result = value;
 	}
 
+	/// Sets N and Z flags per the 8- or 16-bit value @c value; @c shift should be 0 to indicate an 8-bit value or 8 to indicate a 16-bit value.
 	void set_nz(uint16_t value, int shift) {
 		negative_result = uint8_t(value >> shift);
 		zero_result = uint8_t(value | (value >> shift));
 	}
 
+	/// Sets the Z flag per the 8- or 16-bit value @c value; @c shift should be 0 to indicate an 8-bit value or 8 to indicate a 16-bit value.
+	void set_z(uint16_t value, int shift) {
+		zero_result = uint8_t(value | (value >> shift));
+	}
+
 	void set(uint8_t flags) {
 		carry				= flags		& Flag::Carry;
 		negative_result		= flags		& Flag::Sign;
diff --git a/Processors/65816/Implementation/65816Implementation.hpp b/Processors/65816/Implementation/65816Implementation.hpp
index e560877ec..7ed69af32 100644
--- a/Processors/65816/Implementation/65816Implementation.hpp
+++ b/Processors/65816/Implementation/65816Implementation.hpp
@@ -508,6 +508,15 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
 						flags_.set_nz(a_.full, m_shift_);
 					break;
 
+					case BIT:
+						flags_.set_nz(data_buffer_.value & a_.full, m_shift_);
+						flags_.overflow = data_buffer_.value & Flag::Overflow;
+					break;
+
+					case BITimm:
+						flags_.set_z(data_buffer_.value & a_.full, m_shift_);
+					break;
+
 					//
 					// Branches.
 					//
@@ -586,7 +595,7 @@ template <typename BusHandler> void Processor<BusHandler>::run_for(const Cycles
 #undef cp
 
 					// TODO:
-					//	ADC, BIT, SBC,
+					//	ADC, SBC,
 					//	PLP,
 					//	PHP, PHD, PHK,
 					//	TRB, TSB,
diff --git a/Processors/65816/Implementation/65816Storage.cpp b/Processors/65816/Implementation/65816Storage.cpp
index 23d3aee9f..e20e162e2 100644
--- a/Processors/65816/Implementation/65816Storage.cpp
+++ b/Processors/65816/Implementation/65816Storage.cpp
@@ -857,7 +857,7 @@ ProcessorStorage::ProcessorStorage() {
 	/* 0x86 STX d */			op(direct, STX);
 	/* 0x87 STA [d] */			op(direct_indirect_long, STA);
 	/* 0x88 DEY i */			op(implied, DEY);
-	/* 0x89 BIT # */			op(immediate, BIT);
+	/* 0x89 BIT # */			op(immediate, BITimm);
 	/* 0x8a TXA i */			op(implied, TXA);
 	/* 0x8b PHB s */			op(stack_push, PHB);
 	/* 0x8c STY a */			op(absolute, STY);
diff --git a/Processors/65816/Implementation/65816Storage.hpp b/Processors/65816/Implementation/65816Storage.hpp
index c3b13de60..335ccb3dc 100644
--- a/Processors/65816/Implementation/65816Storage.hpp
+++ b/Processors/65816/Implementation/65816Storage.hpp
@@ -137,7 +137,7 @@ enum MicroOp: uint8_t {
 enum Operation: uint8_t {
 	// These perform the named operation using the value in the data buffer;
 	// they are implicitly AccessType::Read.
-	ADC, AND, BIT, CMP, CPX, CPY, EOR, ORA, SBC,
+	ADC, AND, BIT, CMP, CPX, CPY, EOR, ORA, SBC, BITimm,
 
 	// These load the respective register from the data buffer;
 	// they are implicitly AccessType::Read.