6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-09-28 09:54:49 +00:00
Code Issues Projects Releases Wiki Activity

The port input/output flags are now honoured; reading a port that is set as an output returns the current output value.

Browse Source
This commit is contained in:
Thomas Harte 2017-08-07 19:01:18 -04:00
parent 4427e9a254
commit 745afd217f
2 changed files with 7 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Components/AY38910/AY38910.cpp
View File

@ -226,7 +226,11 @@ uint8_t AY38910::get_register_value() {
0xe0, 0xe0, 0xe0, 0x00, 0x00, 0xf0, 0x00, 0x00
};
return registers_[selected_register_] | register_masks[selected_register_];
switch(selected_register_) {
default: return registers_[selected_register_] | register_masks[selected_register_];
case 14: return (registers_[0x7] & 0x40) ? registers_[14] : port_inputs_[0];
case 15: return (registers_[0x7] & 0x80) ? registers_[15] : port_inputs_[1];
}
}
#pragma mark - Port handling
@ -236,7 +240,7 @@ uint8_t AY38910::get_port_output(bool port_b) {
}
void AY38910::set_port_input(bool port_b, uint8_t value) {
registers_[port_b ? 15 : 14] = value;
port_inputs_[port_b ? 1 : 0] = value;
update_bus();
}

1
Components/AY38910/AY38910.hpp
View File

@ -59,6 +59,7 @@ class AY38910: public ::Outputs::Filter<AY38910> {
private:
int selected_register_;
uint8_t registers_[16], output_registers_[16];
uint8_t port_inputs_[2];
int master_divider_;