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https://github.com/TomHarte/CLK.git
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Sketched out an interface for a digial PLL. Not persuaded yet. Baby steps.
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@ -7,6 +7,7 @@
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@ -1861,6 +1866,7 @@
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4B0BE4281D3481E700D5256B /* DigitalPhaseLockedLoop.cpp in Sources */,
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9
Storage/Disk/DigitalPhaseLockedLoop.cpp
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9
Storage/Disk/DigitalPhaseLockedLoop.cpp
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@ -0,0 +1,9 @@
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//
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// DigitalPhaseLockedLoop.cpp
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// Clock Signal
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//
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// Created by Thomas Harte on 11/07/2016.
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// Copyright © 2016 Thomas Harte. All rights reserved.
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//
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#include "DigitalPhaseLockedLoop.hpp"
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Storage/Disk/DigitalPhaseLockedLoop.hpp
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54
Storage/Disk/DigitalPhaseLockedLoop.hpp
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//
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// DigitalPhaseLockedLoop.hpp
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// Clock Signal
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//
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// Created by Thomas Harte on 11/07/2016.
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// Copyright © 2016 Thomas Harte. All rights reserved.
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//
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#ifndef DigitalPhaseLockedLoop_hpp
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#define DigitalPhaseLockedLoop_hpp
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namespace Storage {
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class DigitalPhaseLockedLoop {
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public:
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/*!
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Instantiates a @c DigitalPhaseLockedLoop.
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@param clocks_per_bit The expected number of cycles between each bit of input.
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@param tolerance The maximum tolerance for bit windows — extremes will be clocks_per_bit ± tolerance.
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*/
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DigitalPhaseLockedLoop(unsigned int clocks_per_bit, unsigned int tolerance);
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/*!
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Runs the loop, impliedly posting no pulses during that period.
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@c number_of_cycles The time to run the loop for.
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*/
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void run_for_cycles(unsigned int number_of_cycles);
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/*!
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Announces a pulse at the current time.
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*/
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void add_pulse();
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/*!
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A receiver for PCM output data; called upon every recognised bit.
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*/
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class Delegate {
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public:
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virtual void digital_phase_locked_loop_output_bit(bool value) = 0;
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};
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void set_delegate(Delegate *delegate)
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{
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_delegate = delegate;
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}
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private:
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Delegate *_delegate;
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};
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}
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#endif /* DigitalPhaseLockedLoop_hpp */
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