1
0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-25 01:32:55 +00:00

Add note on provenance.

This commit is contained in:
Thomas Harte 2024-09-08 20:20:03 -04:00
parent 2a9e1ea045
commit 75db0018bc

View File

@ -50,6 +50,12 @@ uint8_t VideoOutput::run_for(const Cycles cycles) {
int number_of_cycles = cycles.as<int>();
while(number_of_cycles--) {
// The below is my attempt at transcription of the equivalent VHDL code in moogway82's
// JamSoftElectronULA — https://github.com/moogway82/JamSoftElectronULA — which is itself
// derived from hoglet67's https://github.com/hoglet67/ElectronFpga and that author's
// reverse-engineering of the Electron ULA. It should therefore be as accurate to the
// original hardware as my comprehension of VHDL and adaptation into sequential code allows.
// Horizontal and vertical counter updates.
const bool is_v_end = v_count_ == v_total();
h_count_ += 8;