From 768f47198f413ec5d30aed19e5b1632fb86d92af Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Thu, 21 Apr 2022 16:10:21 -0400 Subject: [PATCH] Add proper arguments for Bcc, BRA, BSR. --- Processors/68000/Implementation/68000Storage.cpp | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/Processors/68000/Implementation/68000Storage.cpp b/Processors/68000/Implementation/68000Storage.cpp index 6aa47c9c2..72f70aa81 100644 --- a/Processors/68000/Implementation/68000Storage.cpp +++ b/Processors/68000/Implementation/68000Storage.cpp @@ -1119,6 +1119,13 @@ struct ProcessorStorageConstructor { case Quick: if(operation_ == Operation::MOVEq) { sprintf(tbuf, "%d", int8_t(opcode_)); + } else if(operation_ == Operation::Bcc || operation_ == Operation::BRA) { + const int8_t val = int8_t(opcode_); + if(!val) { + return "#"; + } else { + sprintf(tbuf, "%d", val); + } } else { const auto val = ((opcode_ >> 9)&7); sprintf(tbuf, "%d", val ? val : 8); @@ -2077,7 +2084,7 @@ struct ProcessorStorageConstructor { // This decoder actually decodes nothing; it just schedules a PerformOperation followed by an empty step. case Decoder::Bcc_BSR: { const int condition = (instruction >> 8) & 0xf; - dumper.set_source(Imm); + dumper.set_source(Quick); if(condition == 1) { // This is BSR, which is unconditional and means pushing a return address to the stack first. @@ -2093,7 +2100,7 @@ struct ProcessorStorageConstructor { // A little artificial, there's nothing really to decode for BRA. case Decoder::BRA: { op(Action::PerformOperation, seq("n np np")); - dumper.set_source(Imm); + dumper.set_source(Quick); } break; // Decodes a BTST, potential mutating the operation into a BTSTl,