From 76d7e0e1f8c1fcc406ad6abb23166c44cbbfdfeb Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Tue, 19 Apr 2022 16:27:20 -0400 Subject: [PATCH] Test and correct SUBs. --- InstructionSets/68k/Decoder.cpp | 29 ++++++++++--------- .../Mac/Clock SignalTests/m68kDecoderTests.mm | 11 +++++++ 2 files changed, 27 insertions(+), 13 deletions(-) diff --git a/InstructionSets/68k/Decoder.cpp b/InstructionSets/68k/Decoder.cpp index 6d58c62fb..99104859c 100644 --- a/InstructionSets/68k/Decoder.cpp +++ b/InstructionSets/68k/Decoder.cpp @@ -129,7 +129,7 @@ template Preinstruction Predecoder::validated // case EORIb: case EORIl: case EORIw: // case ORIb: case ORIl: case ORIw: // case ANDIb: case ANDIl: case ANDIw: -// case SUBIb: case SUBIl: case SUBIw: + case SUBIb: case SUBIl: case SUBIw: case ADDIb: case ADDIl: case ADDIw: // case CMPIb: case CMPIl: case CMPIw: switch(original.mode<1>()) { @@ -145,10 +145,11 @@ template Preinstruction Predecoder::validated // ADD. case OpT(Operation::ADDb): case OpT(Operation::ADDw): case OpT(Operation::ADDl): + case OpT(Operation::SUBb): case OpT(Operation::SUBw): case OpT(Operation::SUBl): switch(original.mode<0>()) { default: break; case AddressingMode::AddressRegisterDirect: - if constexpr (op != OpT(Operation::ADDb)) { + if constexpr (op != OpT(Operation::ADDb) && op != OpT(Operation::SUBb)) { break; } case AddressingMode::None: @@ -167,6 +168,7 @@ template Preinstruction Predecoder::validated // ADDA. case OpT(Operation::ADDAw): case OpT(Operation::ADDAl): + case OpT(Operation::SUBAw): case OpT(Operation::SUBAl): switch(original.mode<0>()) { default: break; case AddressingMode::None: @@ -210,7 +212,8 @@ template Preinstruction Predecoder::decode(ui // b3: 1 => operation is memory-to-memory; 0 => register-to-register. // case OpT(Operation::ABCD): case OpT(Operation::SBCD): - case OpT(Operation::ADDXb): case OpT(Operation::ADDXw): case OpT(Operation::ADDXl): { + case OpT(Operation::ADDXb): case OpT(Operation::ADDXw): case OpT(Operation::ADDXl): + case OpT(Operation::SUBXb): case OpT(Operation::SUBXw): case OpT(Operation::SUBXl): { const auto addressing_mode = (instruction & 8) ? AddressingMode::AddressRegisterIndirectWithPredecrement : AddressingMode::DataRegisterDirect; @@ -894,11 +897,11 @@ template Preinstruction Predecoder::decode9(uint16_t instruction) { using Op = Operation; - switch(instruction & 0x0c0) { - // 4-174 (p278) - case 0x00: Decode(Op::SUBb); - case 0x40: Decode(Op::SUBw); - case 0x80: Decode(Op::SUBl); + switch(instruction & 0x1f0) { + // 4-184 (p288) + case 0x100: Decode(Op::SUBXb); + case 0x140: Decode(Op::SUBXw); + case 0x180: Decode(Op::SUBXl); default: break; } @@ -911,11 +914,11 @@ Preinstruction Predecoder::decode9(uint16_t instruction) { default: break; } - switch(instruction & 0x1f0) { - // 4-184 (p288) - case 0x100: Decode(Op::SUBXb); - case 0x140: Decode(Op::SUBXw); - case 0x180: Decode(Op::SUBXl); + switch(instruction & 0x0c0) { + // 4-174 (p278) + case 0x00: Decode(Op::SUBb); + case 0x40: Decode(Op::SUBw); + case 0x80: Decode(Op::SUBl); default: break; } diff --git a/OSBindings/Mac/Clock SignalTests/m68kDecoderTests.mm b/OSBindings/Mac/Clock SignalTests/m68kDecoderTests.mm index 193999426..7a9d539f9 100644 --- a/OSBindings/Mac/Clock SignalTests/m68kDecoderTests.mm +++ b/OSBindings/Mac/Clock SignalTests/m68kDecoderTests.mm @@ -101,6 +101,17 @@ template NSString *operand(Preinstruction instruction) { case Operation::ADDXw: instruction = @"ADDX.w"; break; case Operation::ADDXl: instruction = @"ADDX.l"; break; + case Operation::SUBb: instruction = @"SUB.b"; break; + case Operation::SUBw: instruction = @"SUB.w"; break; + case Operation::SUBl: instruction = @"SUB.l"; break; + + case Operation::SUBAw: instruction = @"SUBA.w"; break; + case Operation::SUBAl: instruction = @"SUBA.l"; break; + + case Operation::SUBXb: instruction = @"SUBX.b"; break; + case Operation::SUBXw: instruction = @"SUBX.w"; break; + case Operation::SUBXl: instruction = @"SUBX.l"; break; + // For now, skip any unmapped operations. default: continue; }